JSTS:Journal of Semiconductor Technology and Science

  • 제15권3호
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  • Pages.334-341
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  • 2015
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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The Design of a 0.15 ps High Resolution Time-to-Digital Converter

  • Lee, Jongsuk (School of Electronic Engineering, Soongsil University) ;
  • Moon, Yong (School of Electronic Engineering, Soongsil University)
  • 투고 : 2014.10.12
  • 심사 : 2015.04.17
  • 발행 : 2015.06.30
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초록

This research outlines the design of a HR-TDC (High Resolution Time-to-Digital Converter) for high data rate communication systems using a $0.18{\mu}m$ CMOS process. The coarse-fine architecture has been adopted to improve the resolution of the TDC. A two-stage vernier time amplifier (2S-VTA) was used to amplify the time residue, and the gain of the 2S-VTA was larger than 64. The error during time amplification was compensated using two FTDCs (Fine-TDC) with their outputs. The resolution of the HR-TDC was 0.15 ps with a 12-bit output and the power consumption was 4.32 mW with a 1.8-V supply voltage.

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참고문헌

  1. A. Elshazly, y, R. Inti, B. Young, and P. K. Hanumolu, "A 1.5GHz $890 {\mu}W$ digital MDLL with 400fsrms integrated jitter, -55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDC," IEEE Solid-State Circuit Conference Digest of Technical Papers (ISSCC), pp.242-244, 2012.
  2. Xiaolu Liu, Na Yan, Xi Tan, and Hao Min, "A 0.8ps minimum-resolution sub-exponent TDC for ADPLL in $0.13{\mu}m$ CMOS," IEEE Annual Conference of The Association of Surgeons of India (ASICON), pp.602- 605, Oct. 2011.
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