한국통신학회논문지 (The Journal of Korean Institute of Communications and Information Sciences)

  • 제40권4호
  • /
  • Pages.613-618
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  • 2015
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  • 1226-4717(pISSN)
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  • 2287-3880(eISSN)
한국통신학회 (The Korean Institute of Commucations and Information Sciences)
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저 전력 10비트 플래시-SAR A/D 변환기 설계

Design of a Low Power 10bit Flash SAR A/D Converter

  • Lee, Gi-Yoon (Inha University Department of Electronic Engineering) ;
  • Kim, Jeong-Heum (Inha University Department of Electronic Engineering) ;
  • Yoon, Kwang-Sub (Inha University Department of Electronic Engineering)
  • 투고 : 2014.12.24
  • 심사 : 2015.04.20
  • 발행 : 2015.04.30
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⟨ 이전 논문 다음 논문 ⟩

초록

본 논문은 2단 플래시 A/D 변환기를 이용한 저전력 CMOS 플래시-SAR(successive approximation register)A/D 변환기를 제안한다. 전체 회로 구조는 상위 2비트 고속 플래시 A/D 변환기, 하위 8비트 저 전력 SAR A/D 변환기로 구성되어서 데이터 변환 클럭 수를 감소시켜서 변환속도를 향상시켰다. 또한 하위 8비트를 SAR 논리회로와 커패시터 D/A 변환기를 이용하여 저 전력으로 회로를 설계하였다. 제안 된 A/D 변환기는 $0.18{\mu}m$ CMOS 공정을 이용하여 구현하였고 2MS/s의 변환속도를 갖으며 9.16비트의 ENOB(effective number of bit)이 측정되었다. 면적과 전력소모는 각각 $450{\times}650{\mu}m^2$와 $136{\mu}W$이고 120fJ/step의 FoM을 갖는다.

This paper proposed a low power CMOS Flash-SAR A/D converter which consists of a Flash A/D converter for 2 most significant bits and a SAR A/D converter with capacitor D/A converter for 8 least significant bits. Employment of a Flash A/D converter allows the proposed circuit to enhance the conversion speed. The SAR A/D converter with capacitor D/A converter provides a low power dissipation. The proposed A/D converter consumes $136{\mu}W$ with a power supply of 1V under a $0.18{\mu}m$ CMOS process and achieves 9.16 effective number of bits for sampling frequency up to 2MHz. Therefore it results in 120fJ/step of Figure of Merit (FoM).

키워드

참고문헌

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