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Design of a LDO regulator with a protection Function using a 0.35 µ BCD process

0.35 ㎛ BCD 공정을 이용한 보호회로 기능이 추가된 모바일용 LDO 레귤레이터

  • Lee, Min-Ji (Department of Nano System Engineering, Inje University) ;
  • Son, Hyun-Sik (Department of Nano System Engineering, Inje University) ;
  • Park, Young-Soo (Department of Electronics Engineering Chung Cheong University) ;
  • Song, Han-Jung (Department of Nano System Engineering, Inje University)
  • 이민지 (인제대학교 나노시스템공학과) ;
  • 손현식 (인제대학교 나노시스템공학과) ;
  • 박용수 (충청대학교 전기전자학부) ;
  • 송한정 (인제대학교 나노시스템공학과)
  • Received : 2014.08.11
  • Accepted : 2015.01.08
  • Published : 2015.01.31

Abstract

We designed of a LDO regulator with a OVP and UVLO protection function for a PMIC. Proposed LDO regulator circuit consists of a BGR reference circuit, an error amplifier and a power transistor and so on. The proposed LDO regulator is designed for low voltage input power protection. Proposed LDO circuit generated fixed 2.5 V from a supply of 3.3V. It was designed with 3.3 V power supply using a $0.35{\mu}m$ CMOS technology. SPICE simulation results showed that the proposed circuit provides 0.713 mV/V line regulation with output 2.5 V ~ 3.9 V and $8.35{\mu}V/mA$ load regulation with load current 0 mA to 40 mA.

본 논문에서는 고속 PMIC(Power Management Integrated Circuit) 회로를 위한 저전압 입력 보호기능을 가지는 모바일용 LDO(Low Drop-Out) 레귤레이터를 설계하였다. 설계된 LDO 레귤레이터는 밴드갭 기준전압회로, 오차 증폭회로, 파워 트랜지스터 등으로 이루어진다. LDO 레귤레이터는 3.3 V 전원전압으로부터 2.5 V 출력을 갖도록 설계되었으며, 저전압 입력보호 기능을 하는 UVLO 회로는 전원부와 파워 트랜지스터 사이에 삽입된다. 또한 UVLO는 3.3 V 구동전압에서, 하강시 1.2 V 에서 LDO 레귤레이터 동작을 멈추게 하고, 구동전압 상승 시 2.5 V 에서 LDO 레귤레이터가 정상 동작한다. $0.35{\mu}m$ 5 V 저전압 CMOS 공정을 사용하여 모의실험 한 결과, 설계한 LDO 레귤레이터는 0.713 mV/V의 라인레귤레이션을 가지고, 부하전류가 0 mA에서 40 mA로 변할 때 $8.35{\mu}V/mA$의 로드레귤레이션을 보였다.

Keywords

References

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