DOI QR코드

DOI QR Code

카본 CCL이 적용된 PCB의 열거동 및 신뢰성 특성 연구

A Study on Thermal Behavior and Reliability Characteristics of PCBs with a Carbon CCL

  • 투고 : 2015.11.10
  • 심사 : 2015.12.29
  • 발행 : 2015.12.30

초록

본 논문에서는 HDI(High Density Interconnection) 기판의 코어로 사용될 수 있는 카본 CCL(Copper Claded Layer)의 열거동 및 신뢰성 특성을 실험과 CAE를 이용한 수치해석을 통해 평가하였다. 카본 CCL의 특성평가를 위해 기존 FR-4 코어와 heavy cu 코어와 비교하였다. 연구결과에 의하면 pitch계열 카본코어가 적용된 PCB의 휨강도가 가장 높고 온도에 따른 변형량이 가장 낮았다. 또한, HDI 신뢰성평가 기준의 TC(Thermal Cycling), LLTS(Liquid-to-Liquid Thermal Shock), Humidity 실험을 통해 카본코어가 적용된 PCB는 신뢰성이 확보되었음을 확인하였다. 카본 파이버에 의한 불균일한 비아홀의 표면형상 여부와 드릴비트 마모 가능성을 분석하였는데 비아홀의 표면은 균일하고, 드릴비트의 표면도 매끄러워 카본 CCL의 우수한 드릴가공성도 확인하였다.

In this paper, the Thermal behavior and reliability characteristics of carbon CCL (Copper Claded Layer), which can be used as the core of HDI (High Density Interconnection) PCB (Printed Circuit Board) are evaluated through experiments and numerical analysis using CAE (Computer Aided Engineering) software. For the characterization of the carbon CCL, it is compared with the conventional FR-4 core and Heavy Cu core. From research results, the deformation amount of the flexure strength of PCB is the highest with pitch grade carbon and thermal behavior of PCB is lowest as temperature increases. In addition, TC (Thermal Cycling), LLTS (Liquid-to-Liquid Thermal Shock) and Humidity tests have been applied in the PCB with carbon core and the reliability of PCB with carbon core is confirmed through reliability tests. Also, possibility of uneven surface of the via hole and wear of the drill bit due to the carbon fibers are analyzed. surface of the via hole is uniform, the surface of the drill bit is smooth. Therefore, it is proved that the carbon CCL has the drilling workability of the same level as conventional core material.

키워드

참고문헌

  1. M. Y. Tsi, C. H. J. Hsu, and C. T. O. Wang, "Investgation of thermomechanical behaviors of flip chip BGA packages during manufacuring process and thermal cycling", IEEE Trans. Compon. Pack.-Technol. 27(3), 568 (2004). https://doi.org/10.1109/TCAPT.2004.831817
  2. J. Liu, C. P. Wang, and J. L. Prince, "Electronic Packaging: Design, Materials, Process, and Reliability", McGraw-Hill, New York (1997).
  3. R. Darveaux, C. Reichman, and N. Islam, "Interface Failure in Lead Free Solder Joints", Proc. 56th Electronic Components and Technology Conference (ECTC) (2006).
  4. Seunghyun Cho, S. J. Cho, and J. Y. Lee, "Estimation of warpage and thermal stress of IVHs in flip-chip ball grid arrays package by FEM", Microelectron Reliab., 48(2), 300, (2008). https://doi.org/10.1016/j.microrel.2007.06.001
  5. J. H. Lau and S.-W. R. Lee, "Effects of Build-Up Printed Circuit Board Thickness in the Solder Joint Reliability of a Wafer Level Chip Scale Package (WLCSP)", Trans. Comp. Packag. Technol., 25(1), 3 (2002). https://doi.org/10.1109/6144.991169
  6. S. H. Cho, H. I. Jung, and O. C. Bae, "Numerical Analysis on the Design Variables and Thickness Deviation Effects on Warpage of Substrate for FCCSP", J. Microelectron. Packag. Soc., 19(3), 57 (2012). https://doi.org/10.6117/kmeps.2012.19.3.057
  7. W. Sun, W. H. Zhu, C. K. Wang, A. Y. S. Sun, and H. B. Tan, "Warpage Simulation and DOE Analysis with Application in Package-on-Package Development", 9th. Int. Conf. on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems, EuroSimE, 1 (2008).
  8. Y. L. Tzeng, N. Kao, E. Chen, J. Y. Lai, Y. P. Wang, and C. S. Hsiao, "Warpage and Stress Characteristic Analyses on Package-on-Package (PoP) Structure", 9th Electronics Packaging Technology Conference (EPTC), Singapore, 482, IEEE (2007).
  9. W. Sun, W. H. Zhu, K. S. Le, and H. B. Tan, "Simulation Study on the Warpage Behavior and Board-level Temperature Cycling Reliability of PoP Potentially for High-speed Memory Packaging", International Conference on Electronic Packaging Technology & High Density Packaging (ICEPT-HDP 2008), Shanghai, 1, IEEE (2008).
  10. S. H. Cho, D. H. Kim, Y. J. Oh, J. T. Lee, and S. S. Cha, "A Study on the Parameters of Design for Warpage reduction of Passive components Embedded Substrate for PoP", J. Microelectron. Packag. Soc., 22(1), 75 (2015). https://doi.org/10.6117/kmeps.2015.22.1.075
  11. S. H. Cho and J. Y. Lee, "Heat dissipation of printed circuit board by the high thermal conductivity of photo-imageable solder resist", Electronic materials letters., 6(4), 167 (2011). https://doi.org/10.3365/eml.2010.12.167
  12. S. H. Cho, "Heat dissipation effect of Al plate embedded substrate in network system", Microelectronics Reliability, 48, 1696 (2008). https://doi.org/10.1016/j.microrel.2008.04.018
  13. X. J. Fan, "Combined thermal and thermomechanical modeling for a multichip QFN package with metal-core printed circuit board", The Ninth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), 2. 377, IEEE (2004).
  14. X. J. Fan and S. Haque, "Emerging MOSFET packaging technologies and their thermal evaluation", Proc. 8th ASME/IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), San Diego, 1102 (2002).
  15. MARC 2014 user manual, Volume A : Theory and user information, (2014).