원자로 제어시스템 FPGA 개발에 사용되는 상용 합성도구의 COTS 인증

  • 발행 : 2015.07.17

초록

키워드

참고문헌

  1. International Electrotechnical Commission, IEC 61226, "Nuclear Power PIlants - Instrumentation And Control Systems Important For Safety - Classification," 1994.
  2. 이준구, 정광일, 박근옥, 손광영, "HRD 개발수명주기를 적용한 원전 FPGA 기반 제어기의 설계와 검증," 한국전자통신학회 논문지, Vol. 9, No. 5, 2014.
  3. Jong Gyun Choi, Dong Young Lee, "Development of RPS Trip Logic Based on PLD Technology," Nuclear Engineering and Technology, vol. 44, no. 6, pp.697-708, 2012. https://doi.org/10.5516/NET.04.2011.004
  4. Junbeom Yoo, Jong-Hoon Lee and Jang-Soo Lee, "A Research on Seamless Platform Change of Reactor Protection System from PLC to FPGA," Nuclear Engineering and Technology, Vol. 45, No. 4, pp.477-488, 2013. https://doi.org/10.5516/NET.04.2012.078
  5. J. She, "Investigation on the benefits of safety margin improvement in CANDU nuclear power plant using an FPGA-based shutdown system," Ph.D. dissertation, The University of Western Ontario, 2012.
  6. Nuclear Regulatory Commission, NUREG/CR-6421, "A Proposed Acceptance Process for Commercial Off-the-Self(COTS) Software in Reactor Applications," 1996.
  7. Electric Power Research Institute, "Plant Engineering: Guidelines for the Acceptance of Commercial-Grade Items in Nuclear Safety-Related Applications," 2013.
  8. Electric Power Research Institute, "Guideline on Evaluation and Acceptance of Commercial Grade Digital Equipment for Nuclear Safety Applications," 1996
  9. KINS, "KINS/RG-N17.12," http://scaie.kins.re.kr/service/main/main.do
  10. 배창호, 이동희, 김규로, 장중순, "원전용 디지털 인디케이터의 검증 규정 EPRI TR-106439 에 관한 고찰," Vol. 15, No. 4, pp. 248-255, 2014.
  11. T. Hoare, "The verifying compiler: A grand challenge for computing research," Jownal of the ACM, Vol.50, No.1, pp.63-69, 2003.
  12. Leroy X. "Formal Verification of a Realistic Compiler," Communication of the ACM 2000, Vol. 52, No.7, pp.107-115, 2000. https://doi.org/10.1145/1538788.1538814
  13. Huang SY, Cheng KT. Fromal Equivalence Checking and Design Debugging, chap. 4. Kliwer Academic Publishers, 1998.
  14. Institute of Electrical and Electronics Engineers, "IEEE Standard Verilog Hardware Description Language," 2001.
  15. Institute of Electrical and Electronics Engineers, "IEEE Standard VHDL Language Reference Manual," 2008.
  16. Mentor Graphics Corporation, "HDL Designer SeriesTM User Manual," Tech. Rep., 2008.
  17. Esterel Technologies, www.esterel-technologies.com/products/scade-suite/, 2007
  18. Mentor Graphics, "ModeISim," http://www.mentor.com/products/fv/modelsim/.
  19. Synopsys, "Synopsys synplify pro," http://www.synopsys.com/Tools/.
  20. Mentor Graphics, "Precision RTL," http://www.mentor.com/products/fpga/synthesis/precision_rtI.
  21. Cadence, "Encounter RTL Compiler," http://www.cadence/products/ld/rtl_compiler/pages/default.aspx/.
  22. Mentor Graphics, "FormaIPro," http://www.mentor.com/products/fv/formalpro/.
  23. Cadence, "Encounter Conformal LEC," http://www.cadence.com/products/ld/equivalence
  24. Synopsys, "Formaiity," http://www.synopsys.com/tools/verification/formalequivalence/pages/formality.aspx/.
  25. Brayton RK, Hachtel GD, Sangiovanni-Vincentelli A, Somenzi F, Aziz A, Cheng ST, Edwards SA, Khatri SP, Kukimoto Y, Pardo A, et al.. VIS : A system for verification and synthesis. the Eighth International Conference on Computer Aided Verification, CAV '96, 1996; 428-432.
  26. Wikipedia, "Static timing analysis," https://en.wikipedia.org/wiki/Static_timing_analysis
  27. Xilinx. Xilinx ise design suite. http://www.xilinx.com/products/.
  28. Actel, "Actel libero ide," http://www.actel.com/products/software/.
  29. Altera. Altera quartus ii. http://www.altera.com/products/software/.