Journal of Computing Science and Engineering

  • 제9권4호
  • /
  • Pages.177-189
  • /
  • 2015
  • /
  • 1976-4677(pISSN)
  • /
  • 2093-8020(eISSN)
한국정보과학회 (Korean Institute of Information Scientists and Engineers)
권호 표지
DOI QR코드

DOI QR Code

Exploiting Static Non-Uniform Cache Architectures for Hard Real-Time Computing

  • Ding, Yiqiang (Department of Electrical and Computer Engineering, Virginia Commonwealth University) ;
  • Zhang, Wei (Department of Electrical and Computer Engineering, Virginia Commonwealth University)
  • 투고 : 2015.09.14
  • 심사 : 2015.11.19
  • 발행 : 2015.12.30
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

High-performance processors using Non-Uniform Cache Architecture (NUCA) are increasingly used to deal with the growing wire delays in multicore/manycore processors. Due to the convergence of high-performance computing with embedded computing, NUCA caches are expected to benefit high-end embedded systems as well. However, for real-time systems that use multicore processors with NUCA caches, it is crucial to bound worst-case execution time (WCET) accurately and safely. In this paper, we developed a WCET analysis approach by considering the effect of static NUCA caches on WCET. We compared the WCET in real-time applications with different topologies of static NUCA caches. Our experimental results demonstrated that the static NUCA cache could improve the worst-case performance of realtime applications using multicore processor compared to the cache with uniform access time.

키워드

참고문헌

  1. C. Kim, D. Burger, and S. W. Keckler, "An adaptive, nonuniform cache structure for wire-delay dominated on-chip caches," in Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), San Jose, CA, 2002, pp. 211-222.
  2. J. Yan and W. Zhang, "WCET analysis for multi-core processors with shared L2 instruction caches," in Proceedings of 14th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'08), St. Louis, MO, 2008, pp. 80-89.
  3. Y. Li, V. Suhendra, Y. Liang, T. Mitra, and A. Roy-choudhury, "Timing analysis of concurrent programs running on shared cache multi-cores," in Proceedings of 30th IEEE Real-time System Symposium (RTSS), Washington, DC, 2009, pp. 57-67.
  4. M. Lv, W. Yi, N. Guan, and G. Yu, "Combining abstract interpretation with model checking for timing analysis of multicore software," in Proceedings of 31st IEEE International Real-Time System Symposium (RTSS), San Diego, CA, 2010, pp. 339-349.
  5. T. Kelter, H. Falk, P. Marwedel, S. Chattopadhyay, and A. Roychoudhury, "Bus-aware multicore WCET analysis through TDMA offset bounds," in Proceedings of the 23rd Euromicro Conference on Real-Time Systems (ECRTS), Porto, Portugal, 2011, pp. 3-12.
  6. S. Chattopadhyay, L. K. Chong, A. Roychoudhury, T. Kelter, P. Marwedel, and H. Falk, "A unified WCET analysis framework for multi-core platforms," in Proceedings of IEEE 18th Real-Time and Embedded Technology and Applications Symposium (RTAS), Beijing, China, 2012, pp. 99-108.
  7. Y. Ding and W. Zhang, "WCET analysis of static NUCA caches," in Proceedings of the 33rd IEEE International Performance Computing and Communications Conference (IPCCC), Austin, TX, 2014, pp. 1-6.
  8. W. Zhang and J. Yan, "A unified timing analysis approach for shared caches of multicores," in Proceedings of the Work-in-Progress (WIP) session of 17th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), Chicago, IL, 2011.
  9. W. Zhang and J. Yan, "Static timing analysis of shared caches for multicore processors," Journal of Computing Science and Engineering, vol. 6, no. 4, pp. 267-278, 2012. https://doi.org/10.5626/JCSE.2012.6.4.267
  10. Y. S. Li and S. Malik, "Performance analysis of embedded software using implicit path enumeration," in Proceedings of the ACM SIGPLAN 1995 Workshop on Languages, Compilers, & Tools for Real-Time Systems (LCT-RTS 1995), La Jolla, CA, 1995, pp. 88-98.
  11. Y. S. Li, S. Malik, and A. Wolfe, "Performance estimation of embedded software with instruction cache modeling," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 1995, pp. 380-387.
  12. Y. S. Li, S. Malik, and A. Wolfe, "Cache modeling for realtime software: beyond direct mapped instruction caches," in Proceedings of the 17th IEEE Real-Time Systems Symposium (RTSS'96), Washington, DC, 1993, pp. 254-263.
  13. C. A. Healy, R. D. Arnold, F. Mueller, D. Whalley, and M. G. Harmon, "Bounding pipeline and instruction cache performance," IEEE Transactions on Computers, vol. 48, no. 1, pp. 53-70, 1999. https://doi.org/10.1109/12.743411
  14. Homepage of CPLEX, http://www.ilog.com/products/cplex/.
  15. Malardalen WCET Research Group, Malardalen WCET benchmark suite, http://www.mrtc.mdh.se/projects/wcet.