IEMEK Journal of Embedded Systems and Applications (대한임베디드공학회논문지)

Institute of Embedded Engineering of Korea (대한임베디드공학회)
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PCM Main Memory for Low Power Embedded System

저전력 내장형 시스템을 위한 PCM 메인 메모리

  • Received : 2015.05.28
  • Accepted : 2015.08.05
  • Published : 2015.12.31
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Abstract

Nonvolatile memories in memory hierarchy have been investigated to reduce its energy consumption because nonvolatile memories consume zero leakage power in memory cells. One of the difficulties is, however, that the endurance of most nonvolatile memory technologies is much shorter than the conventional SRAM and DRAM technology. This has limited its usage to only the low levels of a memory hierarchy, e.g., disks, that is far from the CPU. In this paper, we study the use of a new type of nonvolatile memories - the Phase Change Memory (PCM) with a DRAM buffer system as the main memory. Our design reduced the total energy of a DRAM main memory of the same capacity by 80%. These results indicate that it is feasible to use PCM technology in place of DRAM in the main memory for better energy efficiency.

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References

  1. Samsung Elec., DRAM, http://www.samsung.com/global/business/semiconductor
  2. B.S. Jung, J.H. Lee, "Analysis on the Effectiveness of the Filter Buffer for Low Power NAND Flash Memory," IEMEK J. Embed. Syst. Appl., Vol. 7, No. 4, pp. 201-207, 2012 (in Korea). https://doi.org/10.14372/IEMEK.2012.7.4.201
  3. K.S. Jung, J.W. Pack, C.C. Weems, S.D. Kim, "A Superblock-based Memory Adapter Using Decoupled Dual Buffers for Hiding the Access Latency of Non-volatile Memory," Proceedings of the World Congress on Engineering and Computer Science, pp. 19-21, 2011.
  4. J. Dong, L. Zhang, Y. Han, X. Li, "Ear rate leveling : lifetime enhancement of pram with endurance variation," Proceedings of Design Automation, pp. 972-977, 2011.
  5. H.G. Lee, "High-performance NAND PRAM Hybrid Storage Design for Consumer Electronics," IEEE Transactions on Comsumer Electronic, Vol. 56, No. 1, pp. 112-118, 2010. https://doi.org/10.1109/TCE.2010.5439133
  6. L.A. Barroso. "The Case for Energy Proportional Computing," Journal of Computer, Vol. 40, No. 12, pp. 33-37, 2007.
  7. G. Dhiman, R. Ayoub, T. Rosing, "PDRAM : A Hybrid PRAM and DRAM Main Memory System," Proceedings of The 46th Annual Design Automation Conference, pp. 664-669, 2009.
  8. M.K. Qureshi, J. Karidis, M. Franceschini, V. Srinivasan, L. Lastras, B. Abali, "Enhancing Lifetime and Security of PCM-Based Main Memory with Start-Gap Wear Leveling," Proceedings of The 42nd Annual IEEE/ACM International Symposium on Microarchitecture, pp. 14-23, 2009.
  9. P. Zhou, B. Zhao, J. Yang, Y. Zhang, "A Durable and Energy Efficient Main Memory Using Phase Change Memory Technology," Proceedings of The 36th Annual International Symposium on Computer Architecture, pp. 14-23, 2009.
  10. G.S. Choi, B.W. On, K.H. Choi, S.W. Yi, "PTL: PRAM translation layer," Journal of Microprocessors & Microsystems, Vol. 37, No. 1, pp. 24-32, 2013. https://doi.org/10.1016/j.micpro.2012.07.002
  11. N. Lu, I.S. Choi, S.H. Ko, S.D. Kinm, "An Effective Hierarchical PRAM-SLC-MLC Hybrid Solid State Disk," Proceedings of The 11th International Conference on Computer and Information Science, pp. 113-118, 2012.
  12. B.C. Lee, E. Ipek, O. Mutlu, D. Burger, "Architecting phase change memory as a scalable dram alternative," Proceedings of The 36th Annual International Symposium on Computer Architecture, pp. 2-13, 2009.
  13. D. Burger, T. Austin, "The SimpleScalar tool set, version 3.0," http://www.simplescalar.com/
  14. M. Bian, S. Yoon, S. Kim, "A Memory-Disk Integrated Non-volatile Memory System with its Dual Buffering Adapter," High-Performance Computer Architecture, pp. 1-9, 2013.