References
- W. M. Reddick et al., "Silicon surface tunnel transistor," Appl. Phys. Lett., vol. 67, 1995, p. 494-497. https://doi.org/10.1063/1.114547
-
K. K. Bhuwalka et al., "Performance enhancement of vertical tunnel field-effect transistor with SiGe in the
${\delta}$ p+ layer," Jpn. J. Appl. Phys., vol. 43, 2004, p. 4073-4078. https://doi.org/10.1143/JJAP.43.4073 - J. Appenzeller et al., "Band-to-band tunneling in carbon nanotube field-effect transistors," Phys. Rev. Lett., vol. 93, 2004, p. 196805-1-196805-4. https://doi.org/10.1103/PhysRevLett.93.196805
- Q. Zhang et al., "Low-subthreshold-swing tunnel transistors," IEEE Electron Device Lett., vol. 27, 2006, p. 297-300. https://doi.org/10.1109/LED.2006.871855
- W. Y. Choi et al., "Tunneling field-effect transistor (TFETs) with subthreshold swing (SS) less than 60 mV/dec," IEEE Electron Device Lett., vol. 28, 2007, p. 743-745. https://doi.org/10.1109/LED.2007.901273
- K. Jeon et al., "Si tunnel transistors with a novel silicied source and 46 mV/dec swing," in VLSI Tech. Symp. On., 2010, p. 121-122.
- W. Y. Choi et al., "Hetero-gate-dielectric tunneling field-effect transistors," IEEE Trans. Electron Devices, vol. 57, 2010, p. 2317-2319. https://doi.org/10.1109/TED.2010.2052167
- T. Krishnamohan et al., "Double-gate strained-Ge heterostructure tunneling FET (TFET) with record high drive currents and <<60 mV/dec subthreshold slope," in IEDM Tech. Dig., 2012, p. 1-3.
- K. Kao et al., "Direct and indirect band to band tunneling in germanium based TFETs," IEEE Trans. Electron Devices, vol. 59, 2012, p. 292-301. https://doi.org/10.1109/TED.2011.2175228
- H. W. Kim et al., "Investigation on suppression of nickel-silicide formation by flouorocarbon reactive ion etch (RIE) and plasma-enhanced deposition." Journal of Semiconductor Technology & Science, vol. 13, 2013, pp. 22-27. https://doi.org/10.5573/JSTS.2013.13.1.022
- J. P. Kim, "Asymmetric MOSFETs using novel fabrication method." Ph. D. Dissertation, Department of Electrical, Seoul National University, 2010.
- S.-J. Choi et al., "High injection efficiency and low-voltage programming in a dopant segregated Schottky barrier (DSSB) FinFET SONOS for NOR-type flash memory," IEEE Electron Device Lett., vol. 30, 2009, p. 256-268.
- A. Chattopadhyay et al., "Impact of a spacer dielectric and a gate overlap/underlap on the device performace of a tunnel field-effect transistor," IEEE Trans. Electron Devices, vol. 58, 2011, p. 677-683. https://doi.org/10.1109/TED.2010.2101603
Cited by
- A 1T-DRAM cell based on a tunnel field-effect transistor with highly-scalable pillar and surrounding gate structure vol.69, pp.3, 2016, https://doi.org/10.3938/jkps.69.323
- Reconfigurable U-shaped tunnel field-effect transistor vol.14, pp.20, 2017, https://doi.org/10.1587/elex.14.20170758