한국산학기술학회논문지 (Journal of the Korea Academia-Industrial cooperation Society)

  • 제15권9호
  • /
  • Pages.5744-5749
  • /
  • 2014
  • /
  • 1975-4701(pISSN)
  • /
  • 2288-4688(eISSN)
한국산학기술학회 (The Korea Academia-Industrial cooperation Society)
권호 표지
DOI QR코드

DOI QR Code

배타 논리합 원리를 이용한 다출력 논리회로 간략화

Multioutput Logic Simplication Using an Exclusive-OR Logic Synthesis Principle

  • 권오형 (한서대학교 컴퓨터공학과)
  • 투고 : 2014.08.07
  • 심사 : 2014.09.11
  • 발행 : 2014.09.30
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

다출력 논리식에서 공통식을 추출하는 것은 매우 중요한 기술이다. 본 논문에서는 배타 논리합 식 산출 원리를 이용해서 공통식을 추출하는 새로운 방법을 제안하였다. 산출된 논리식은 AND, OR, NOT 연산자만을 이용해서 전체 논리식을 표현하도록 고안하였다. 공통식 산출의 수행 시간과 리터럴 개수를 줄이기 위해서 선험 방법을 제안하였다. 실험 결과 제안한 방법이 기존의 방법들보다 리터럴 개수를 줄일 수 있음을 보였다.

An extraction technique for a common logic expression is an extremely important part of multiple-output logic synthesis. This paper presents a new Boolean extraction technique using an exclusive-OR logic synthesis principle. The logic circuits produced only have AND, OR and NOT gates. Heuristic methods can also be applied to reduce the execution time and the number of literals. The experimental results showed improvements in the literal counts over the previous methods.

키워드

참고문헌

  1. R. K. Brayton and C. McMullen, "The Decomposition and Factorization of Boolean Epressions." Proc. ISCAS, pp. 49-54, 1982.
  2. R. K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. R. Wang, " MIS: A Multiple-Level Logic Optimization System." IEEE Trans. CAD, Vol. 6, No. 6, pp. 1062-1081, 1987. DOI: http://dx.doi.org/10.1109/TCAD.1987.1270347
  3. E. M. Sentovich, K. J. Singh, C. Moon, H. Savoj, R. K. Brayton, R. K., and A. Sangiovanni-Vincentelli, "Sequential Circuit Design Using Synthesis and Optimization." Proc. ICCD, pp. 328-333, 1992.
  4. J. Rajski and J. Vasudevamurthy, "The testability-preserving concurrent decomposition and factorization of Boolean expressions," IEEE Trans. CAD, Vol. 11, No. 6, pp. 778-79, 1992. DOI: http://dx.doi.org/10.1109/43.137523
  5. D. Wu and J. Zhu, "BDD-based Two Variable Sharing Extraction," Proc. of Asia and South Pacific Design Automation Conference(ASPDAC), pp. 1031-1034, 2005.
  6. O.-H. Kwon,, "Common Expression Extraction Using Kernel-Kernel pairs," Journal of the Korea Academia-industrial cooperation Society, Vol. 12, No. 7, pp. 3251-3257, 2011. DOI: http://dx.doi.org/10.5762/KAIS.2011.12.7.3251
  7. O.-H. Kwon,, "Common Expression Extraction Using Two-cube Qoutient Matrices," Journal of the Korea Academia-industrial cooperation Society, Vol. 12, No. 8, pp. 3715-3722, 2011. DOI: http://dx.doi.org/10.5762/KAIS.2011.12.8.3715
  8. O.-H. Kwon,, "Common Expression Extraction Using Supports in Multiple-Output Logic," Journal of the Korea Institure of Information Technology, Vol. 9, No. 11, pp. 17-25, 2011.
  9. M. Morrison and N. Ranganathan, "Synthesis of Dual-Rail Adiabatic Logic for Low Power Security Applications," IEEE Trans. CAD, Vol. 33, No. 7, pp. 975-988, 2014. DOI: http://dx.doi.org/10.1109/TCAD.2014.2313454