한국정보통신학회논문지 (Journal of the Korea Institute of Information and Communication Engineering)

  • 제18권9호
  • /
  • Pages.2176-2182
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  • 2014
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  • 2234-4772(pISSN)
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  • 2288-4165(eISSN)
한국정보통신학회 (The Korea Institute of Information and Commucation Engineering)
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개선된 전원 잡음 제거를 위한 전원 전압 감지용 위상 고정 루프의 설계

Design of Phase Locked Loop with Supply Noise Detector for Improving Noise Reduction

  • Choi, Hyek-Hwan (Department of Electronics Engineering, Pukyung National University) ;
  • Choi, Young-Shig (Department of Electronics Engineering, Pukyung National University)
  • 투고 : 2014.05.30
  • 심사 : 2014.07.15
  • 발행 : 2014.09.30
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초록

이 논문에서는 기존의 위상고정루프에 전원 잡음 제거 회로를 추가한 위상고정 루프 회로를 제안한다. 제안한 구조는 주파수 전압 변환기를 변형한 전원 잡음 제거 회로를 사용하여 임의의 전원 잡음에 대해 보상하여 동작한다. 전원 잡음 제거 회로를 사용하여 전원 잡음에 의해 발생하는 지터의 크기를 1/3로 줄였다. 제안한 위상 고정 루프는 0.18um CMOS 공정을 사용 하여 HSPICE 시뮬레이션을 통해 예측되는 결과를 검증하였다.

In this paper, a phase locked loop with suppressed power supply noise has been proposed. The added negative feedback loop of voltage controlled oscillator(VCO) and power noise detector suppresses the power noise induced jitter variation of VCO down to 1/3. The power noise detector is the modified circuit of frequency voltage converter. The proposed PLL has been designed based on a 1.8V 0.18um CMOS process and proved by HSPICE simulation.

키워드

참고문헌

  1. F. Herzel and B. Razavi, "A Study of Oscillator Jitter due to Supply and Substrate Noise", IEEE Trans, Circuits Syst. II, vol. 46, no. 1, pp. 56-62, Jan. 1999. https://doi.org/10.1109/82.749085
  2. A. A. Abidi, "Phase Noise and Jitter in CMOS Ring Oscillators," IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1803-1816, Aug. 2006. https://doi.org/10.1109/JSSC.2006.876206
  3. V. von Kaenal, D. Aebischer, C. Piguet, and D. Dijkstra, "A 320MHz, 1.5 mW @ 1.35V CMOS PLL for Microprocessor Clock Generation" IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1715-1722, Nov. 1996. https://doi.org/10.1109/JSSC.1996.542316
  4. K. Chang, J. Wei, C. Huang, S. Li, K. Donnelly, M. Horowitz, and S. Sidiropoulos, "A 0.44-Gb/s CMOS Quad Transceiver Cell using on-chip Regulated Dual-Loop PLLs" IEEE J. Solid-State Circuits, vol. 38, no. 5, pp. 747-754, May 2003. https://doi.org/10.1109/JSSC.2003.810045
  5. S. Sidiropoulos, D. Liu, J. Kim, G. Wei, and M. Horowitz, "Adaptive Bandwidth DLLs and PLLs using Regulated Supply CMOS Buffers" in Symp. VLSI Circuits Dig., 2000. pp. 124-127.
  6. E. Alon, J. Kim, S. Pamati, K. Chang, and M. Horowitz, "Replica Compensated Linear Regulators for Supply-Regulated Phase-LOcked Loops" IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 413-424, Feb. 2006. https://doi.org/10.1109/JSSC.2005.862347
  7. A. Arakali, S. Gondi, and P. K. Hanumolu "Low-Power Supply-Regulation Techniques for Ring Oscillators in Phase-Locked Loops uisng a Split-Tuned Architecture" IEEE J. Solid-State Circuits, vol. 44, no. 8, pp. 2169-2181, Aug. 2009. https://doi.org/10.1109/JSSC.2009.2022916
  8. A. Elshazlyi, R. Inti, W. Yin, B. Young, and P. K. Hanumolu "A 0.4-to-3 GHz Digital PLL with PVT Insensitive Supply Noise Cancellation using Deterministic background Calibration" IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 2759-2771, Dec. 2011. https://doi.org/10.1109/JSSC.2011.2162912
  9. B. Kim, W. Xu and Chris H. Kim "A Supply-Noise Sensitivity Tracking PLL in 32 nm SOI Featuring a Deep trench Capacitor Based Loop Filter" IEEE J. Solid-State Circuits, vol. 49, no. 4, pp. 1017-1026, Apr. 2014. https://doi.org/10.1109/JSSC.2013.2294323