마이크로전자및패키징학회지 (Journal of the Microelectronics and Packaging Society)

  • 제21권2호
  • /
  • Pages.23-29
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  • 2014
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  • 1226-9360(pISSN)
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  • 2287-7525(eISSN)
한국마이크로전자및패키징학회 (The Korean Microelectronics and Packaging Society)
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3차원 패키징용 TSV의 열응력에 대한 열적 전기적 특성

A study on Electrical Characteristic and Thermal Shock Property of TSV for 3-Dimensional Packaging

  • 정일호 (서울시립대학교 신소재공학과) ;
  • 기세호 (서울시립대학교 신소재공학과) ;
  • 정재필 (서울시립대학교 신소재공학과)
  • Jeong, Il Ho (Dept. of Materials Science and Engineering University of Seoul) ;
  • Kee, Se Ho (Dept. of Materials Science and Engineering University of Seoul) ;
  • Jung, Jae Pil (Dept. of Materials Science and Engineering University of Seoul)
  • 투고 : 2014.01.04
  • 심사 : 2014.06.16
  • 발행 : 2014.06.30
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초록

Less power consumption, lower cost, smaller size and more functionality are the increasing demands for consumer electronic devices. The three dimensional(3-D) TSV packaging technology is the potential solution to meet this requirement because it can supply short vertical interconnects and high input/output(I/O) counts. Cu(Copper) has usually been chosen to fill the TSV because of its high conductivity, low cost and good compatibility with the multilayer interconnects process. However, the CTE mismatch and Cu ion drift under thermal stress can raise reliability issues. This study discribe the thermal stress reliability trend for successful implementation of 3-D packaging.

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참고문헌

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피인용 문헌

  1. Cu Through-Via Formation using Open Via-hole Filling with Electrodeposition vol.21, pp.4, 2014, https://doi.org/10.6117/kmeps.2014.21.4.117
  2. Effect of Via Pitch on the Extrusion Behavior of Cu-filled TSV vol.56, pp.6, 2018, https://doi.org/10.3365/KJMM.2018.56.6.449
  3. A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process vol.11, pp.10, 2021, https://doi.org/10.3390/met11101664