A Novel Circuit for Characteristics Measurement of SiC Transistors

Abstract

This paper proposes a novel test circuit for SiC transistors. On-state resistance under practical application conditions is an important characteristic for the device reliability and conduction efficiency of SiC transistors. In order to measure the on-state resistance in practical applications, high voltage is needed, and high current is also necessary to ignite performance for the devices. A soft-switching circuit based on synchronous buck topology is developed in this paper. To provide high-voltage and high-current stresses for the devices without additional spikes and oscillations, a resonant circuit has been introduced. Using the novel circuit technology, soft-switching can be successfully realized for all the switches. Furthermore, in order to achieve accurate measurement of on-state resistance under switching operations, an active clamp circuit is employed. Operation principle and design analysis of the circuit are discussed. The dynamic measurement method is illustrated in detail. Simulation and experiments were carried out to verify the feasibility of the circuit. A special test circuit has been developed and built. Experimental results confirm that the proposed circuit gives a good insight of the devices performance in real applications.

1. Introduction

Silicon-carbide (SiC) transistors are gaining popularity for their enormous potential [1-4]. Recent demonstrations show that SiC transistors can attain outstanding properties such as higher electron density, lower drain-to-source onresistance, lower thermal resistance, and higher breakdown voltage in comparison to silicon (Si) counterparts [5-10]. Although much progress has been achieved in the development of new power devices, power converters that employ SiC transistors have not become commercially available, because device performance issues under switching operation have not been sufficiently discussed yet [11-14].

To improve these promising next-generation power devices, it is also highly desirable to evaluate the characteristics, such as on-state resistance, during device measurements, especially under realistic power electronics conditions [15-17].

The traditional method to characterize on-state resistance is the pulse I-V step measurement, which is shown in Fig. 1. This technique requires special equipment and cannot mimic the actual applications. However, few research papers have been produces to measure dynamic on-state resistance of the new devices over the past years [18-20]. In [18] a VIENNA boost converter to character the GaN transistors under operating condition is developed using a Wilson current mirror based circuit to measure dynamic drain-to-source voltage of the devices. The converter can be used to measure dynamic on-state resistance, gate charge, miller charge, and switching time, etc. But the clamp voltage contains a spike at the transition to the offstate of the switching device. In [20] a voltage clamp circuit using power MOSFET and zener diode is presented. This technique can test GaN transistors in soft-switching and hard-switching conditions. However, the measured dynamic drain-to-source voltage can be influenced by the auxiliary MOSFET body diode and its application is limited.

Fig. 1.The traditional method to measure on-state resistance.

In addition, to evaluate a power switch under actual switching operation [5, 20, 21], the extreme conditions (e.g., high voltage and high current) should be implemented. Unfortunately, simultaneously high voltage and current power supply (e.g., 400V/50A) in a test laboratory are difficult due to the limited capacity of power installation. Furthermore, reproduction of high voltage and current stresses by means of direct testing should be confronted with huge equipment.

In this paper, a novel and effective measurement technique for SiC transistors has been presented which involves typical equipment. This proposed technique could reproduce the voltage and current stresses equal to or greater than those which meet in real applications by employing common power supplies. This is one of the merits of the proposed test circuit. To avoid the measurement saturation of oscilloscope, a new and simple voltage clamp circuit is developed with achieving accurate measurement of onstate resistance, which is another merit of the circuit. The proposed circuit gives a good insight of devices performance in real applications. Simulation and experimental results under extreme conditions confirm the validity of the proposed circuit.

This paper is organized as follows. Section II describes the operation principle and detailed analysis of the circuit. Section III discusses the design procedure of the proposed circuit. Section IV explains the measurement method of the on-state resistance. Section V features the simulation and experimental results. Finally, conclusions are presented in Section VI.

 

2. Circuit Configuration and Operation

2.1 Circuit configuration

The configuration of the proposed circuit is shown in Fig. 2. The main structure of the circuit is based on a synchronized buck converter which is designed to operate in discontinuous inductor current mode (DCM).

Fig. 2.The proposed test circuit.

The test system consists of a voltage source VH , an upper side Si power MOSFET QH , a current source VL , an ultra-fast diode D, an LC filter, an active voltage clamp circuit, and DUT (device under test), where QH , D, LC filter and the DUT compose the basic synchronized buck converter.

In the configuration, CQaux and CDUT are denoted as the equivalent output capacitances of Qaux and QDUT, respectively, which consist of the drain-to-source and snubber capacitance of each switch. The high side MOSFET, QH, and the DUT operate complementarily with a variable dead-time. The auxiliary Si MOSFET, Qaux, operates synchronously with the DUT. The series LC filter together with a damping power resistor RL is connected to the positive terminal of the low voltage high current power supply VL directly.

As the same with conventional synchronized buck converter, the main function of QH is to provide high voltage stress during the off-state of the DUT. The diode D is used to provide a free-wheeling path for the inductance current iLr, to impede high voltage stress from VH, and the most important, to supply high current stress to the DUT. The main function of the inductor Lr is to absorb the energy stored in the output capacitance of QDUT, Qaux, and D to realize soft switching by resonance during transitions. The capacitor CR is used to store the energy delivered by Lr and prevent any potential DC voltage from VH to VL.

As shown in Fig. 2, R1 is denoted as a thermally protected fusing resistor for over-current protection of VH. R2 is a low value power resistor to limit the current stress of DUT. In the conventional synchronized buck converter, RL is the load of the converter, consuming a lot of power. However, it should be noted that in this proposed circuit, as the inductor is designed much smaller than the critical conduction mode value, the power consumed by RL can be considerable small. Therefore, the extra voltage and current stresses incurred by the LC filter and RL can be neglected.

The voltage clamp circuit consists of the auxiliary switch Qaux and the blocking capacitor Cclamp, which are parallel with the DUT. The measurement principle of the circuit will later be illustrated in Section III.

2.2 Circuit operation principles

To understand the voltage and current stresses of the DUT and to analyze the switching characteristic in detail, it is necessary to explain the operation principles of the circuit and some important equations during transitions.

To simplify the analysis, it is assumed that all the switching devices are ideal except the above illustration. The capacitance of CR is assumed large enough so that the voltage on it, denoted as VCR, stays constant approximately. As the inductor is operated in DCM, the inductance current iLr would change direction before the next switching cycle.

The operation of the circuit can be divided into eight main stages in one switching period. The signal control sequence of the switches and the corresponding key waveforms of the operation are illustrated in Fig. 3. Fig. 4 shows the conduction path and current direction in every transition. The detailed analysis of this converter will be thoroughly examined in the following.

Fig. 3.Theoretical waveforms of the proposed circuit.

Fig. 4.Equivalent circuits for each operation mode: (a) Stage 1 [t0 - t1]; (b) Stage 2 [t1 - t2]; (c) Stage 3 [t2 - t3]; (d) Stage 4 [t3 - t4]; (e) Stage 5 [t4 - t5]; (f) Stage 6 [t5 - t6]; (g) Stage 7 [t6 - t7]; (h) Stage 8 [t7 - t8].

Stage 1 [t0 - t1] [see Fig. 4(a)]: This stage begins at t0 when the high side switch, QH, is in on state and the high voltage is applied to Lr and CR. The inductance current iLr increases linearly from zero with the ramp rate controlled by the VH and Lr, ending at a peak current value iL(t1). The inductance value is designed big enough that iLr increases slowly with a very small average value. The DUT and Qaux are in off state so that high voltage stress is applied to DUT. The voltage across Cclamp is clamped at a low level value as there is no current circulation through Qaux, which is the main function of the voltage clamp circuit. VCR is charged up by the inductor current. The inductance current iL(t) and the drain-to-source voltage of DUT vDS_DUT(t) are given by

In this stage, the current stress of the DUT is zero.

Stage 2 [t1 - t2] [see Fig. 4(b)]: This stage starts by turning QH off, and thus, vDS_H begins to increase. Because of the dead-time between gate driver signals, DUT and Qaux are still in off state. As shown in Fig. 4(b), VL is lower than the voltage across the DUT. The diode current iDiode cannot flow and D is reverse biased. A resonance starts among Lr, Cclamp, CQaux, CDUT, and CQH. Due to the resonant nature, when vDS_DUT decreases to VL+VCR at time ta, the inductance current iLr reaches to its maximum value iLMax. As a result, iLr first increases and then decreases in a very short period. In addition, the DUT current iDUT continues to flow through its output capacitance CDUT until vDS_DUT is equal to VL. Along with the decreasing of vDS_DUT, the clamped voltage vclamp also decreases. During the interval [t1 - ta], iLr and vDS_DUT are expressed as

where iLMax is the resonant peak value of iLr , Z0 is the equivalent impedance of the resonant circuit,

As for the interval time [ta - t2], the voltage applied to DUT decreases from VL+VCR. This stage period t12 is

Stage 3 [t2 - t3] [see Fig. 4(c)]: Once vDS_DUT reaches VL at time t2, diode D is forward biased and provides a freewheeling path for the inductance current and the resonance process is stopped. During this stage, the voltage applied to QH, vDS_H, is kept at VH−VL+VD. Meanwhile, the energy associated with Lr is drawn to the “load” resistor RL. As a result, the inductance current iLr decreases at a slow rate. The time of this stage is prescribed by the dead-time control. The voltage stress of QDUT is

where VD is the forward voltage of the diode D. The current stress of QDUT is zero within this period.

Stage 4 [t3 - t4] [see Fig. 4(d)]: At time t3, the DUT and Qaux are turned on synchronously. Since the voltage VL–VD is much lower than VH, the switches are operated under ZVS approximately. The high current stress supplied by VL are applied to the DUT. By proper design of auxiliary circuit and gate driver timing, as discussed in the next section, the clamped voltage applied to Cclamp, vclamp, goes closely approximate to vDS_DUT in a high precision. Within this period, the inductance current iLr continues flowing through the diode and decreasing linearly. The drain-tosource voltage of QH increases to VH–vDS_DUT. At the end of this interval, iLr falls down to zero. During this stage, the voltage and current stresses across to DUT can be expressed as:

and

respectively, where rDS(on) is the dynamic on resistance of the DUT.

Stage 5 [t4 - t5] [see Fig. 4(e)]: At time t4, the inductance current iLr reverse its polarity and starts to increase from zero. As the DUT and Qaux are still in on state during this period, the diode D continues conducting with a very low impedance, indicating that the inductance current iLr will mainly flow through D rather than DUT. Therefore, the influence of iLr to iDS_DUT can be neglected, especially when iDS_DUT is much bigger than iLr. In this interval, the voltage and current stresses to the DUT are the same with Stage 4. The inductance current iLr is given by

Stage 6 [t5 - t6] [see Fig. 4(f)]: This stage starts by turning the DUT and Qaux off. Due to the existence of CQaux and CDUT, the switches are turned off under ZVS. As there is a dead-time, QH keeps off in this stage. Once DUT is turned off, the diode D starts the reverse recovery process in a very short interval, after which a resonance occurs among Lr, Cclamp, CQaux, CDUT, and CQH. Thus, Cclamp, CQaux and CDUT are charged while CQH is discharged. At time tb, vDS_DUT increases to VL+VCR, and the inductance current iLr reaches to its maximum value i’LMax in the opposite direction. Therefore, the inductance current iLr first increases and then decreases after a very short period. Meanwhile, as the capacitance Cclamp is much bigger than CQaux, the clamped voltage vclamp are kept in a very low level comparing with vDS_DUT. The voltage stress applied to the DUT equals to the capacitance voltage of CDUT, which is given by

As the resonant circuit constitution in this stage is the same with in Stage 2, we can get that iLMax= i’LMax. Comparing with VH and VCR, VL is significantly small, thus, the parasitic capacitors’ charging time from 0 to VL is very short and can be neglected. In addition, since iLr is considerable small, current stress of the DUT in this stage can be neglected. This stage period t56 can be expressed as

The inductance current iLr is given by

Stage 7 [t6 - t7] [see Fig. 4(g)]: At time t6, the voltage of CDUT is charged up to VH and the drain-to-source voltage of QH falls down to zero. Thus, the body diode of QH starts to conduct and provides a freewheeling path to the inductance current iLr. The resonance process ends at t6, and therefore, iLr decreases linearly with a small average value

As a result, during this period, the voltage stress of the DUT is given by

and the current stress is zero. In addition, the clamped voltage vclamp is kept at its maximum value.

Stage 8 [t7 - t8] [see Fig. 4(h)]: QH is turned on at time t7. Since the body diode is in on state, the switch is operated under ZVS. The high voltage stress VH+iL(t)R1 is still applied to the DUT and the voltage clamp circuit. The freewheeling path of the inductance current iLr changes to QH from the body diode.

This stage ends when the inductance current iLr reaches zero and begins to increase in the opposite direction. Therefore, at the moment t=t8, one switching cycle is completed and a new switching cycle starts.

 

3. Analysis of the Measuring Stage

In order to improve the reliability and performance of new power devices, the characteristics measurement should be discussed under practical operations. From the principle analysis in the previous section, the proposed circuit can represent real operating circumstances, and gives a good insight into the performance of the devices in practical applications. The proposed system, which is a combination of a regular synchronous buck topology, a low voltage high current power supply, and an active clamp circuit comprising an additional switch and a capacitor, makes it possible to measure various characteristics under real power applications, such as high voltage and high current conditions.

The main circuit can be designed like a regular synchronized buck converter which works in DCM. However, unlike the conventional synchronous buck converter, the main concept of the proposed system is to perform the characteristics measurement of SiC transistors. Therefore, the design considerations have a lot of differences, which are important during measurements, such as operation mode, power capacity, and dead-time of control signals.

To achieve ZVS of the DUT, it is necessary that the energy stored in Lr at the moment QH turning off should be larger than or equal to the energy required to discharge the output capacitance of QH, Qaux and QDUT down to zero.

Furthermore, reduction of the peak voltage and current stresses of the DUT can be achieved by adjusting the inductance current and the dead-time of driving signals. The dead-time is needed to avoid cross conduction between the switches and to realize soft-switching.

From the analysis in Section II, the ZVS conditions can be expressed as:

Therefore, we have

and

During the dead-time the voltage over DUT cannot decrease below input voltage VL. Therefore, the maximum reasonable dead-time is the one that is needed to lower the voltage over the switch to VL level. A longer dead-time would be unnecessary. A certain amount of magnetizing current is required in order to reduce the voltage level over the DUT switch prior to its turn-on.

Based on the superposition theorem and boundary conditions of operation mode of the converter, when operating in critical-conduction-mode (CrM), we can get that

where D is the duty ratio of the CrM converter.

From (21) and (23), the ZVS conditions (18) and (19) can be simplified as:

From the conventional critical inductance design, the maximum value of Lr can be designed as:

where fs is the switching frequency.

In actual applications, waveforms contain spikes and oscillations. In this proposed circuit, it is possible to turn on the main switch at a relatively low voltage level with the help of the series LC filter, and therefore, the influence of peak voltage stress can be reduced.

The electrical performance of the device represents its viability in power applications. SiC transistors are still in a development stage, therefore, there is a good opportunity to study, design, and test not only a device but also the processes involved. This test circuit provides a very helpful tool to get an optimal design.

 

4. Dynamic On-resistance Measurement Method

The measurement method of DUT dynamic onresistance operating in switching mode is based on the Ohms law, being calculated by dividing vDSon by iDS

In real applications, the drain-to-source voltage of the DUT usually swings in a large range such as hundreds of volts in the off-state and several millivolts in the on-state. Direct measurement using oscilloscope voltage probes either gives poor accuracy or causes saturation of the oscilloscope channel. To avoid of these problems, an active clamp circuit is employed in the proposed system to avoid the oscilloscope saturation in off-state.

Fig. 5 presents the equivalent configuration of the active clamp circuit. The operation principle is discussed in Section II and shown in Fig. 3. The output voltage waveform vDS (t) of the DUT is measured between the nodes A and B using a differential probe. Rprobe denotes the impedance of the oscilloscope probe, which is about 1㏁ generally. rQaux and rDSon denote the on-state resistance of Qaux and DUT, respectively.

Fig. 5.Equivalent circuits for for rDS_on measurement: (a) off state; (b) on state.

As shown in Fig. 5(a), when DUT and Qaux are turned off, high voltage stress vDSoff is applied to the DUT and the active clamp circuit. The measured value of the probe can be expressed as follows:

where Zclamp and ZQaux are the equivalent impedance of Cclamp and CQaux, respectively. In the system design, it is easy to achieved that

Therefore, the measured voltage vclampoff can be clamped and approximated as

indicating that the measured result is “clamped” at a considerable small value comparing with vDSoff.

During the on-state of the DUT, as shown in Fig. 5(b), a high current stress is applied to the DUT along with a very small drain-to-source voltage. The measured voltage across Cclamp can be calculated by

where rQaux is very small with only tens of milli-ohm generally. As Zclamp ≫ rQaux, the measured vclampon can be simplified as

which means the measured voltage is extremely close to the real value vDSon.

Assuming that rDSon of the DUT and QH are 90mΩ and 45mΩ, respectively, the output capacitances of Qaux and the DUT are 500pF, Cclamp is 0.1µF, the switching frequency is 50 kHz, and the on-state DUT current is 1A. We can get that during off state,

while during on state

According to the example result, the active clamp circuit can measure the on-state voltage vDSon with a high precision. Meanwhile, because of the clamp capacitor and the synchronous operation with the DUT, the proposed circuit can measure the on-state vDSon dynamically without the influence of high voltage swing. The value of the off-state clamped voltage vclampoff can be adjusted by using different clamp capacitors. Based on (26), the dynamic on-state resistance of the DUT can be calculated with a high precision.

 

5. Simulation and Experimental Results

5.1 Simulation results

Based on the operation analysis, a PSIM model of the proposed system has been developed. A comprehensive simulation was conducted to verify the performance of the test circuit.

In order to examine the proper performance of the rectifier in practical applications, actual semiconductor models of the power devices were employed.

The experimental waveforms are shown in Figs. 6 and Fig. 7. The driver signals, drain-to-source voltages of DUT and QH, and the current waveforms of DUT and Lr are shown in Fig. 6. According to the waveforms, soft-switching is achieved for both of the DUT and QH. It can be observed that the inductance current is small enough that the influence on the DUT current can be insignificant.

Fig. 6.Simulation switching results.

Fig. 7.Simulation results of the on-state resistance measurement circuit.

The simulation waveforms of the voltage clamp circuit are shown in Fig. 7. While the drain-to-source voltage Vds DUT swings between on-state voltages to up to 400V, the clamped voltage Vclamp changes from on-state voltage to around 2.5V. The clamped on-state voltage is 0.770143V which is very close with the real voltage 0.770427V. Therefore, using the voltage clamp circuit, onstate resistance can be circulated in a high precision.

5.2 Experimental results

A prototype of 400V/10A capacity circuit was performed to verify the theoretical analysis of the proposed circuit. The photograph related to the experimental circuit is given in Fig. 8. Some parameters of the prototype circuit are listed in Table 1. A SiC transistor manufactured by ROHM, SCH2090KE, is chosen as the DUT. The key parameters of the device are shown in Table 2 with reference to the device datasheet. To avoid the temperature influence, a big heatsink and two high power fans were employed during experiments, making sure that the device temperature was kept in 28℃ ~ 30℃.

Fig. 8.The prototype of the proposed test circuit.

Table 1.Parameters of the prototype circuit

Table 2.Parameters of DUT in the prototype circuit

Experiments have been carried out to verify the analysis. The switching waveforms of DUT and QH are shown in Figs. 9 and Fig. 10. In Fig. 9, the voltage, current, and control waveforms of the DUT are illustrated. As the same with simulation results, the switches DUT and QH are operated under soft-switching at both turn-on and turn-off.

Fig. 9.Experimental switching waveforms of the proposed circuit. VGS: driver signal of DUT, VDS: drain-tosource voltage of DUT, VDS_H : drain-to-source voltage of QH , IDS: drain-to-source current of DUT.

Fig. 10.Experimental waveforms of the proposed circuit. VGS: driver signal of DUT, VDS: drain-to-source voltage of DUT, VCr: voltage across CR, IL: inductance current.

The measured waveforms of active clamp circuit are given in Fig. 11. To measure the on-state voltage and current accurately and steadily, the switching frequency was set at 50 kHz. And to eliminate the device temperature increasing, the maximum drain-to-source current was set at 6A. According to the waveforms, the auxiliary switch Qaux was activated synchronously with the DUT. During off state of the switches, the clamped voltage vclamp was clamped at lower than 3V, while the actual drain-to-source voltage of the DUT was up to 400 V. During the on state, vclamp can indicate the real value of the DUT voltage.

Fig. 11.Experimental waveforms of active clamped circuit with VGS =18V. VDS: drain-to-source voltage of DUT, Vclamp: clamped voltage across Caux, IDS: drain-to-source current of DUT.

These results were quite similar to those in the previous study where switching waveforms were simulated.

Figs. 12 to Fig. 17 described the experimental results on the rDSon measurement using oscilloscope probe directly and the active clamp circuit. To evaluate the on-state performance of the DUT under different conditions, the gate driver voltages of the DUT were set as 10V, 14V, and 18V, respectively. The voltage range for comparison was set as 0 ~ 100V in the experiments. Because of the measurement resolution problems, the on-state resistance could not be measured in a high accuracy for conventional circuits. Especially, as the drain-to-source voltage increases, the oscilloscope should be set from 0.1V/div to 10V/div. As on-state resistance is usually less than 1Ω, direct oscilloscope measurement leads a big problem of measurement error.

Fig. 12.The comparison results of on-state resistance with VGS = 10V.

Fig. 17.The experimental result measured by the clamp circuit under full range with VGS = 18V.

Fig. 12, Figs. 14, and Fig. 16 compared the measured results through oscilloscope probe and the active clamp circuit. It can be observed that as the drain-to-source voltage increased, the rDSon which was calculated based on using the probe directly drifted significantly. However, the experimental results via the active clamp circuit kept stable with a high resolution. The measurement errors of the oscilloscope probes were up to 30％, 94％, and 150％ under 10V, 14V, and 18V driving voltages, respectively, comparing with the active clamp circuit.

The experimental results under full voltage range of 0 ~ 400V based on the active clamp circuit are shown in Fig. 13, Figs. 15, and Fig. 17. It is shown that under 10V gate voltage, the on-state resistance of DUT varies a little from 0.419Ω to 0.436Ω, while under 14V gate voltage, the resistance varies from 0.1462Ω to 0.1518Ω. Comparing with the value in datasheet, 0.09Ω, under 18V gate voltage, the on-state resistance changes from 0.0942Ω to 0.0979Ω, illustrating that the DUT has a stable on-resistance performance under large voltage range.

Fig. 13.The experimental result measured by the clamp circuit under full range with VGS = 10V.

Fig. 14.The comparison results of on-state resistance with VGS = 14V.

Fig. 15.The experimental result measured by the clamp circuit under full range with VGS = 14V.

Fig. 16.The comparison results of on-state resistance with VGS = 18V.

Consequently, in terms of the on-state resistance measurement, the active clamp circuit is considered as a reasonable and accurate method.

According to the results above, the calculated results are almost identical to those simulated and measured. As a result, it can be clearly seen that the predicted theoretical analysis and operation principles of the proposed circuit are experimentally verified.

 

6. Conclusion

In this study, a novel circuit for SiC transistors characterization measurement has been analyzed in detail. The proposed circuit is based on the conventional synchronous buck converter operating in DCM. By employing two separated normal power supplies, the test system can mimic practical application conditions to test the reliability and performance of the DUT. To overcome the resolution problems when measuring on-state resistance under realistic switching operation, an active clamp circuit is developed. It is observed that the operation principles and the theoretical analysis of the novel circuit are exactly verified by experimental results. It should be noted that the proposed method of this paper could be extended to Gallium Nitride (GaN) devices for current collapse characteristics measurement.