Analysis and Implementation of a New ZVS DC Converter for Medium Power Application

Abstract

This paper presents a new zero voltage switching (ZVS) converter for medium power and high input voltage applications. Three three-level pulse-width modulation (PWM) circuits with the same power switches are adopted to clamp the voltage stress of MOSFETs at $V_{in}/2$ and to achieve load current sharing. Thus, the current stresses and power ratings of transformers and power semiconductors at the secondary side are reduced. The resonant inductance and resonant capacitance are resonant at the transition interval such that active switches are turned on at ZVS within a wide range of input voltage and load condition. The series-connected transformers are adopted in each three-level circuit. Each transformer can work as an inductor to smooth the output current or a transformer to achieve the electric isolation and power transfer. Thus, no output inductor is needed at the secondary side. Three center-tapped rectifiers connected in parallel are used at the secondary side to achieve load current sharing. Compared with the conventional parallel three-level converters, the proposed converter has less switch counts. Finally, experiments based on a 1.44kW prototype are provided to verify the operation principle of proposed converter.

1. Introduction

Recently, high efficiency power converters have been developed for the cloud server power units and telecommunication power units. For medium power applications, two-stage power conversions (AC/DC+DC/DC) are usually adopted to achieve high power quality and stable DC output voltage. Three-phase (380Vrms or 480Vrms) AC / DC converters with power factor correction (PFC) are generally used in the front stage to supply a stable and constant DC bus voltage for the rear stage DC/DC converter. Usually, the DC bus voltage of a three-phase PFC circuit (380Vrms or 480Vrms) is greater than 600V or 800V. Thus, MOSFETs with 500V or 600V voltage stress cannot be adopted in the second stage such as half-bridge and full-bridge circuit topologies. Although high frequency MOSFETs with 900V voltage stress can be used in the rear DC/DC converters to overcome this problem, the high cost and large turn-on resistance are the main drawbacks of the high voltage MOSFETs. Three-level converters/inverters [1-6] have been proposed to use low voltage stress of power switches for high voltage applications. The neutral point diode clamp converters, flying clamp converters or series full-bridge converters have been presented to limit the voltage stress of power switches at one-half of DC bus voltage. In order to increase the circuit efficiency and reduce the power losses, soft switching techniques [7-15] such as active clamp technique, asymmetric pulse-width modulation (PWM) scheme and series resonant technique have been proposed and used in the two-level PWM converters. For medium power and high input voltage applications, three-level zero voltage switching (ZVS) converters [16-19] have been proposed to have the features of low voltage stress of power semiconductors and high circuit efficiency. In these techniques, the leakage inductance of the transformer (or external inductance) and the output capacitance of power switches are resonant at the transition interval. The drain voltage of MOSFETs can be decreased to zero voltage before the MOSFETs are turned on. For high load current applications such as high power battery charger, parallel three-level converters are usually used. However, parallel converters require too many power switches and passive components.

A new soft switching three-level converter with three PWM circuits is presented in this paper. The main features of the proposed converter are ZVS turn-on for all switches, and low current stress of rectifier diodes and transformer windings and less power switches to achieve parallel operation. Three PWM circuits with the same power switches are adopted in the proposed converter to achieve parallel operation. The flying capacitor and clamped diodes can limit the voltage stress of power switches at Vin/2. Three center-tapped rectifiers connected in parallel are used at the secondary side to reduce the current rating of rectifier diodes. The series-connected two transformers are used in each PWM circuit. One transformer works as a forward-type transformer to transfer the input power to output load, and the other transformer works as an inductor to smooth the load current. Thus, no output inductor is needed at the secondary side. Compared with the conventional parallel converter with three three-level PWM circuits, the proposed converter has less switch counts and the current stress of the transformer windings are also decreased. Finally, experiments are provided to demonstrate the performance of the proposed converter.

 

2. Circuit Configuration

Fig. 1 (a) gives the conventional parallel three-level PWM converter for high input voltage and high load current applications. There are twelve power switches, three flying capacitors, six clamped diodes and three power transformers in the primary side. In the secondary side, there are six rectifier diodes and three filter inductors. The drawback of this circuit is too many power components. Fig. 1(b) shows the circuit configuration of the proposed ZVS converter. Cin1 and Cin2 are equal and large enough to share the input voltage vCin1= vCin2= Vin /2. Active switches S1-S4 are MOSFETs with the voltage stresses of S1-S4 are clamped at Vin/2. Cr1-Cr4 are output capacitances of S1-S4, respectively. Cf is the flying capacitor and its voltage equals Vin/2. C1-C3 are the DC blocking capacitances with the average voltages VC1,av= VC2,av= Vin /2 and VC3,av = 0. Lr1-Lr3 are the resonant inductances. Lm1-Lm6 are the magnetizing inductances of the transformers T1-T6, respectively. Da and Db are the clamped diodes. D1-D6 are the rectifier diodes. Ro and Co denote the load resistance and output capacitance. Phase-shift PWM scheme is adopted to regulate the output voltage. S1 and S4 are the leading switches, and S2 and S3 are the lagging switches. The PWM signals of S1 and S4 are complementary each other with a dead time to allow ZVS operation. Similarly, the PWM signals of S2 and S3 are complementary each other. There are three three-level PWM circuits with the same MOSFETs S1-S4, the flying capacitor Cf and the clamped diodes Da and Db in the proposed converter. The first three-level ZVS circuit is shown in Fig. 1(c). The components of circuit 1 include Cin1, Cin2, Da, Db, Cf, S1-S4, Cr1-Cr4, C1, Lr1, T1, T2, D1 and D2. The circuit 2 shown in Fig. 1(d) includes the components of Cin1, Cin2, Da, Db, Cf, S1-S4, Cr1-Cr4, C2, Lr2, T3, T4, D3 and D4 and the circuit 3 shown in Fig. 1(e) includes Cin1, Cin2, Da, Db, Cf, S1-S4, Cr1-Cr4, C3, Lr3, T5, T6, D5 and D6. Circuit 1 and circuit 2 are operated by the phase shift of one-half of switching cycle. Three voltage levels Vin, Vin/2 and 0 are generated on the terminal voltages vab and vbc. However, another three voltage levels Vin/2, 0 and -Vin/2 are generated on the terminal voltage vbd. Since the average capacitor voltages VC1,av=VC2,av=Vin/2 and VC3,av=0, the voltage levels Vin/2, 0 and -Vin/2 are shown on the primary side voltages vp1-vp3. Two series transformers are used in each circuit to smooth the secondary side current of transformer. Each transformer can work as a transformer to achieve electric isolation and power transfer or as an inductor to smooth output current. Thus, no inductor is needed in the output side. The centertapped rectifier is adopted in the secondary side to obtain a stable output voltage Vo with one diode conduction loss. For high load current applications, each circuit supplies one-third of the load power such that the current stresses of the transformer secondary windings, rectifier diodes and inductors are reduced.

Fig. 1.Circuit topology: (a) conventional parallel threelevel converter; (b) proposed new ZVS three-level converter; (c) circuit 1; (d) circuit 2; (e) circuit 3.

 

3. Operation Principle

The key PWM waveforms of the proposed converter are shown in Fig. 2. Some assumptions are made to simplify the system analysis of the proposed converter.

(1) Power semiconductors, S1-S4, D1-D6 and Da-Db, are ideal. (2) Transformers are identical (Lm1=..=Lm6=Lm). (3) Resonant inductances are identical Lr1=Lr2=Lr3=Lr. (4) Lr＜＜Lm(5) Input capacitances Cin1 and Cin2 are equal and large enough to be considered as two voltage sources VCin1=VCin2=Vin/2. (6) Switch output capacitances Cr1=Cr2=Cr3=Cr4=Cr. (7) DC blocking capacitances C1-C3 and flying capacitance Cf are large enough to be treated as constant voltages VC1=VC2=VCf=Vin/2 and VC3=0. (8) The output voltage Vo is constant.

Fig. 2.Key waveforms of the proposed converter.

Based on the on/off states of active switches S1-S4 and diodes Da-Db and D1-D6, there are ten operation modes in the proposed converter in a switching period. The duty cycle of S1-S4 is equal to 0.5. The PWM signals of S2 and S3 are phase-shifted with respective to the PWM signals of S1 and S4. The equivalent circuits of ten operation modes of the proposed converter are shown in Fig. 3. Prior to time t0, S1, S2, D2, D3 and D5 are conducting.

Fig. 3.Operation modes of the proposed converter in a switching cycle: (a) mode 1; (b) mode 2; (c) mode 3; (d) mode 4; (e) mode 5; (f) mode 6; (g) mode 7; (h) mode 8; (i) mode 9; (j) mode 10.

Mode 1 [t0≤t＜t1]: At time t0, switch S1 is turned off. Since iLr1(t0)＜0, iLr2(t0)＞0 and iLr3(t0)＞0, capacitor Cr1 rises from zero voltage and Cr4 decays from Vin/2 via the flying capacitor Cf. The rising slope of the drain-to-source voltage of S1 (or vCr1) is limited by Cr1 and Cr4. Thus, S1 is turned off at ZVS. If the energy stored in Lm1, Lm4 and Lm6 is greater than the energy stored in Cr1 and Cr4, then Cr4 can be discharged to zero voltage. Thus, the ZVS turn-on condition of S4 is expressed as:

At t1, vCr1=Vin/2 and vCr4 declines to zero voltage. The time interval of mode 1 is obtained as:

In order to achieve ZVS turn-on of S4, the time delay td between S1 and S4 must be greater than Δt01.

Mode 2 [t1≤t＜t2]: At time t1, vCr1=Vin/2 and vCr4=0 such that the clamped diode Da is conducting. Since iLr1(t1) is negative and iLr2(t1) and iLr3(t1) are positive, the switch current iS4 is negative and the anti-parallel diode of S4 is conducting. Therefore, S4 can be turned on at this moment to achieve ZVS. The terminal voltages vab=vbc=Vin/2 and vbd=0. Since VC1=VC2=Vin/2 and VC3=0, the primary side voltages vp1=vp2=vp3=0. Thus, rectifier diodes D1-D6 are all conducting in this mode. The magnetizing voltages are vLm1 = vLm3 = vLm5 = nVo and vLm2= vLm4 = vLm6 =-nVo. Diode currents iD1, iD4 and iD6 increase, and iD2, iD3 and iD5 decrease. If the voltage drop on diode Da and switch S2 are considered in this mode, the slopes of the primary side currents iLr1-iLr3 are expressed as:

where VS2,drop and VDa,drop are the voltage drop on switch S2 and diode Da, respectively. The slopes of the diode currents are given as:

where n=np/ns is the turns ratio of T1-T6. If the voltage drop on S2 and diode Da can be neglected, then the primary currents iLr1-iLr3 and diode currents iD1-iD6 are unchanged in this mode.

Mode 3 [t2≤t＜t3]: At time t2, S2 is turned off. Since iLr1(t2) is negative and iLr2(t2) and iLr3(t2) are positive, Cr2 rises from zero voltage and Cr3 decays from Vin/2 via Cf. The rising slope of vCr2 is limited by Cr2 and Cr3. Thus, S2 is turned off at ZVS. Since the rectifier diodes D1-D6 are still conducting, the magnetizing voltages vLm1=vLm3=vLm5=nVo and vLm2=vLm4=vLm6=−nVo. If the energy stored in Lr1-Lr3 is greater than the energy stored in Cr2 and Cr3, then Cr3 can be discharged to zero voltage. Thus, the ZVS turn-on condition of S3 is given as:

At time t3, vCr3 declines to zero voltage. The time interval in mode 3 is expressed as:

The time delay td between S2 and S3 must be greater than Δt23 in order to achieve ZVS turn-on of S3.

Mode 4 [t3≤t＜t4]: At time t3, Cr3 is discharged to zero voltage. Since iS3(t3)=iLr1(t3)−iLr2(t3)-iLr3(t3) is negative, the anti-parallel diode of S3 is conducting. Thus, S3 can be turned on at this moment to achieve ZVS. In this mode, the voltages vab=Vin, vbc=0, vbd=−Vin/2, vp1=Vin/2 and vp2=vp3=−Vin/2. Since the rectifier diodes D1-D6 are still conducting, the primary side voltages vLm1+vLm2=vLm3+vLm4=vLm5+vLm6=0. Thus, the inductor voltages vLr1=Vin/2 and vLr2=vLr3=−Vin/2. The slopes of the inductor currents and the diode currents in this mode are given as:

At time t4, diode currents iD2, iD3 and iD5 are decreased to zero. In this mode, no power is transferred from input voltage source Vin to output load Ro. Thus, the duty loss in mode 4 is expressed as:

where Ts and fs are the switching period and switching frequency, respectively.

Mode 5 [t4≤t＜t5]: At time t4, diode currents iD2, iD3 and iD5 are decreased to zero. T1, T4 and T6 are working as the forward type transformers and T2, T3 and T5 are working as the inductors to smooth the load current. The voltages vp1=Vin/2 and vp2=vp3=−Vin/2 in this mode. Therefore, the primary current iLr1 increases with the applied Vin/2 and iLr2 and iLr3 decrease with the applied voltage −Vin/2 in this mode.

Power is delivered from input voltage source Vin to output load Ro through D1, D4 and D6 in this mode.

Mode 6 [t5≤t＜t6]: At time t5, switch S4 is turned off. Since iLr1(t5) is positive and iLr2(t5) and iLr3(t5) are negative, Cr1 is discharged and Cr4 is charged via capacitor Cf. The rising slope of the drain-to-source voltage of S4 is limited by Cr1 and Cr4 such that S4 is turned off at ZVS. If the energy stored in Lm2, Lm3 and Lm5 is greater than the energy stored in Cr1 and Cr4, then Cr1 can be discharged to zero voltage. Thus, the ZVS turn-on condition of S1 is expressed as:

At time t6, vCr1=0 and vCr4=Vin/2. The time interval in mode 6 is obtained as:

The time delay td between S1 and S4 should be greater than time interval Δt56 in order to turn on S1 at ZVS.

Mode 7 [t6≤t＜t7]: At time t6, vCr1=0 and vCr4=Vin/2 such that the clamped diode Db is conducting. Since iLr1(t6) is positive and iLr2(t6) and iLr3(t6) are negative, the switch current iS1 is negative and the anti-parallel diode of S1 is conducting. Switch S1 can be turned on at this moment to achieve ZVS. The AC terminal voltages vab=vbc=Vin/2, vbd=0 and vLm1+vLm2=vLm3+vLm4=vLm5+vLm6=0. Thus, the rectifier diodes D1-D6 are conducting. The slopes of the primary side currents are expressed as:

where VS3,drop and VDb,drop are the voltage drop on switch S3 and diode Db, respectively. The slopes of the diode currents are given as:

Diode currents iD1, iD4 and iD6 decrease, and iD2, iD3 and iD5 increase in this mode.

Mode 8 [t7≤t＜t8]: At time t7, switch S3 is turned off. In this mode, Cr2 is discharged and Cr3 is charged. Since the rising slope of vCr3 is limited by Cr2 and Cr3, S3 is turned off at ZVS. Rectifier diodes D1-D6 are still conducting, the magnetizing voltages vLm1 = vLm3 = vLm5 = nVo and vLm2 = vLm4 = vLm6 = −nVo. If the energy stored in Lr1-Lr3 is greater than the energy stored in Cr2 and Cr3, then Cr2 can be discharged to zero voltage. Thus, the ZVS turn-on condition of S2 is given as:

At time t8, vCr2=0 and vCr3=Vin/2. The time interval of mode 8 is expressed as:

The time delay td between S2 and S3 must be greater than time interval Δt78 in order to turn on S2 at ZVS.

Mode 9 [t8≤t＜t9]: At time t8, Cr2 is discharged to zero voltage. Since iS2(t8)=iLr2(t8)+iLr3(t8)-iLr1(t8)＜0, the antiparallel diode of S2 is conducting. S2 can be turned on at this moment to achieve ZVS. The AC side voltages vab=0, vbc=Vin, vbd=Vin/2, vp1=−Vin/2 and vp2=vp3=Vin/2. Since D1-D6 are still conducting and vLm1+vLm2=vLm3+vLm4=vLm5+vLm6=0, the inductor voltages vLr1=−Vin/2 and vLr2=vLr3=Vin/2. The slopes of the inductor currents and the diode currents in this mode are given as:

At time t9, the diode currents iD1, iD4 and iD6 are decreased to zero. The duty loss of mode 9 is expressed as:

Mode 10 [t9≤t＜t0+Ts]: At time t9, iD1=iD4=iD6=0. T2, T3 and T5 are working as the forward type transformers and T1, T4 and T6 are working as the inductors to smooth the load current. The voltages vp1=−Vin/2 and vp2=vp3=Vin/2 in this mode. The primary current iLr1 decreases and iLr2 and iLr3 increase in this mode.

This mode ends at t0+Ts when S1 is turned off. The circuit operations of the proposed converter in a switching period are completed.

 

4. Circuit Characteristics

The time intervals in modes 1, 3, 6 and 8 are much less than the time intervals in the other modes. Thus, only modes 2, 4, 5, 7, 9 and 10 are considered in the following discussions. In modes 2 and 7, the average flying capacitor voltage VCf can be obtained as Vin/2. Based on the voltsecond balance on the primary side of T1-T6, the average capacitor voltages VC1,av=VC2,av=Vin/2 and VC3,av=0. Applying the volt-second balance on Lm1, the output voltage can be expressed as:

where VD is the voltage drop on diodes D1-D6, and δ is the duty ratio of the proposed converter when S1 and S2 are both in the on-state. If the circuit components are given, then the duty ratio δ is related to the input voltage Vin and the load current Io. In steady state, the average diode currents of D1-D6 are equal to Io/6. The ripple inductor current ΔiLr1 in mode 10 can be expressed as:

where r is the ripple current ratio of load current. From (19) and (20), the magnetizing inductance Lm of T1-T6 is given as:

The maximum diode currents iD1,max-iD6,max are expressed as:

Since the average currents on capacitances C1-C3 are zero, the average magnetizing currents ILm1-ILm6 equal zero. In modes 5 and 10, the voltage stresses of D1-D6 are expressed as:

The peak currents, root-mean-square (rms) currents and voltage stresses of switches S1-S4 are given as:

In mode 10, the inductor currents iLr1(t0)-iLr3(t0) (or iLr1(Ts+t0)-iLr3(Ts+t0)) are expressed as:

In mode 2, the inductor currents iLr1(t2)-iLr3(t2) are given as:

Based on (1) and (10), the necessary resonant inductance Lr to achieve ZVS turn-on of S1 and S4 is given as:

From (5) and (14), the necessary inductance Lr to achieve ZVS turn-on of S2 and S3 is given as:

 

5. Design Example and Experimental Results

A prototype circuit with the design procedure is provided in this section. The specifications of the prototype circuit are Vin=550-600V, Vo=24V, and Io=60A. The circuit efficiency is assumed to be 90％. The switching frequency is fs=100kHz. The maximum duty cycle of vp1-vp3 is equal to 0.5 at the minimum input voltage Vin=550V and the full load condition. The maximum duty cycle loss in mode 4 or 9 is assumed 10％ under a full load with a duty cycle δ=0.5.

From (29), the resonant inductance of Lr can be obtained as :

Thus, the resonant inductances Lr1-Lr3 are selected as 40𝜇H in the prototype circuit. If the voltage drop VD on diodes D1-D6 can be neglected, the turns ratio of T1-T6 can be given as:

A TDK EER-42 magnetic core with Ae=1.94cm2 was used to design the transformers T1-T6. The primary turns of T1-T6 with ΔB=0.2T are given as:

The actual primary and secondary winding turns are np=37 and ns=9, respectively and the magnetizing inductances of T1-T6 are 520𝜇H. Based on (24), the rms currents and voltage stresses of S1-S4 are given as:

The IRFP460 MOSFETs with VDS=500V, ID,rms=20A, RDS,on=0.27Ω and Coss=480pF at 25V are used for switches S1-S4. The average currents and voltage stresses of D1-D6 are given as:

The KCU30A30 fast recovery diode with VRRM=300V and IF=30A are used as the rectifier diodes D1-D6. The selected clamped diodes Da and Db are 30ETH06. The selected DC blocking capacitances, flying capacitance and output capacitance are Ca=Cb=470𝜇F, Cf=0.2𝜇F, C1=C2=C3=0.1𝜇F and Co=3000𝜇F. The equivalent output capacitance Cr at Vin=600V is given as:

From (27) and (28), it is clear that ZVS load range of S1 and S4 is wider than the ZVS range of S2 and S3. Thus, only ZVS load range of S2 and S3 is considered in the circuit design. The resonant inductance Lr is obtained in (30). From (28), the minimum inductance current to achieve ZVS turn-on of S2 and S3 is given as:

If the riple currents on primary side and voltage drops on switches and rectifier diodes in (26) are neglected to simplfy the system analysis, then the minimum load current to achieve ZVS can be approximately obtained as :

It means that the power switches S1-S4 can be turned on under ZVS from 6.53A load (about 10％ load) to 60A load (100％ load) in the theoretical analysis. However, there are some riple currents on primary sides and voltage drops on switches and rectifier diodes. Thus, the actual ZVS load range is less than the theoretical ZVS load range in this prototype circuit based on Lr=40𝜇H. If the less resonant inductance is used, i.e. Lr＜40𝜇H, then there is a less duty loss in modes 4 and 9 in this prototype. Thus, the large turns ratio of T1-T6 is obtained and the primary side rms current is decreased. The conduction loss on power MOSFETs is decreased. However, the ZVS load range is also decreased.

Experimental Results based on a laboratory prototype with the circuit parameters derived in the previous section are provided to verify the theoretical analysis of the proposed converter. The measured waveforms of gate voltages of S1-S4, primary side voltages vab-vbd and primary side currents iLr1-iLr3 at low input voltage Vin=550V and different load conditions are shown in Fig. 4. Three voltage levels are generated on vab, vbc and vbd. If S1 and S2 are in the on-state, the primary side current iLr1 decreases and iLr2 and iLr3 increase. On the other hand, iLr1 increases and iLr2 and iLr3 decrease if S1 and S2 are in the off-state. In the same manner, Fig. 5 gives the measured waveforms of gate voltages, primary side voltages and currents at high input voltage Vin=600V and different load conditions. From Figs. 4 and 5, the phase shift between S1 and S2 at Vin=600V is greater than the phase shift at Vin=550V. Therefore, primary side voltages vab, vbc and vbd at Vin=600V have less duty cycle to transfer power from input voltage Vin to output load Ro. The measured waveforms of the gate voltage and drain voltage of the leading switch S1 and the lagging switch S2 at 25％ load and 100％ load for different input voltages are shown in Figs. 6 and 7. It is clear that the leading and lagging switches S1 and S2 are both turned on at ZVS from 25％ load to full load. The voltage stress of S1 and S2 is equal to Vin/2. Since the operation behaviors of S3 and S4 are identical with respective to S2 and S1, it is clear that S3 and S4 realize ZVS turn-on from 25％ load to 100％ load. Figs. 8 and 9 illustrate the experimental waveforms of the DC blocking voltages vC1-vC3 and the flying capacitor voltage vCf at 25％ load and 100％ load for different input voltages. The average capacitor voltages of vC1, vC2 and vCf are equal to Vin/2 and the average capacitor voltage vC3 is equal to zero. Figs. 10 and 11 give the test results of the diode currents at the secondary side for different loads and different input voltage cases. The output currents iD1+iD2, iD3+iD4 and iD5+iD6 from three PWM circuits are balanced. Fig. 12 gives the measured circuit efficiencies of the proposed converter and conventional parallel three-level converter at different input voltages and load conditions. At high input voltage case, there are less conduction losses on power semiconductors such that the measured circuit efficiency at Vin =600V is higher than the efficiency at Vin = 550V case. The proposed converter has less power components compared to the conventional parallel converter such that the measured circuit efficiency in the proposed converter is better than the circuit efficiency in conventional parallel three-level converter.

Fig. 4.Measured results of the gate voltages of S1-S4, the primary side voltages and currents at Vin=550V full load and (a) 25％ load; (b) full load.

Fig. 5.Measured results of the gate voltages of S1-S4, the primary side voltages and currents at Vin=600V full load and (a) 25％ load; (b) full load.

Fig. 6.Measured waveforms of the gate voltage and drain voltage of switches S1 and S2 at Vin=550V and (a) 25％ load (b) full load.

Fig. 7.Measured waveforms of the gate voltage and drain voltage of switches S1 and S2 at Vin=600V and (a) 25％ load (b) full load.

Fig. 8.Measured waveforms of the DC blocking voltages vC1-vC3 and the flying capacitor voltage vCf at Vin= 550V and (a) 25％ load (b) full load.

Fig. 9.Measured waveforms of the DC blocking voltages vC1-vC3 and the flying capacitor voltage vCf at Vin=600V and (a) 25％ load; (b) full load.

Fig. 10.Measured waveforms of the rectifier diode currents at Vin=550V and (a) 25％ load; (b) full load.

Fig. 11.Measured waveforms of the rectifier diode currents at Vin=600V and (a) 25％ load; (b) full load.

Fig. 12.Measured circuit efficiencies of the proposed converter at different input voltages and load conditions.

 

6. Conclusion

A new three-level ZVS converter with three PWM circuits sharing the same power switches is presented in this paper. The main advantages of the proposed converter are 1) ZVS turn-on for all active switches from 25％ to 100％ load, 2) low voltage stress of MOSFETs with onehalf of input voltage, 3) no output filter inductors using series-connected transformers, and 4) low current stress of transformer windings and rectifier diodes using three centertapped circuit topologies. The output voltage is regulated with the phase-shift PWM scheme. The energy stored in the resonant inductance and magnetizing inductance is used to turn on the leading switches at ZVS. However, only the energy stored in the resonant inductance is used to turn on the lagging switches at ZVS. Compared with the conventional parallel three-level converter, the proposed converter has less switch counts and output filter inductors. The system analysis, operation mode and design considerations of the proposed converter are discussed in detail. Finally, experiments with 1.44kW prototype are provided to demonstrate the effectiveness of the proposed converter.