정보과학회지 (Communications of the Korean Institute of Information Scientists and Engineers)

한국정보과학회 (Korean Institute of Information Scientists and Engineers)
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임베디드 응용 가속화를 위한 재구성 프로세서 기술

  • 발행 : 2014.05.16
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초록

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참고문헌

  1. H. Amano, A Survey on Dynamically Reconfigurable Processors, IEICE Transactions, Vol. E89-B, No. 12, 2006.
  2. R. Hartenstein, M. Hertz, Th.Hoffman, and U. Nageldinger, Mapping applications onto reconfigurable Kress- Arrays, Proceedings of Field Programmable Logic and Applications(FPL), 1999.
  3. M. Taylor, J. Kim, J. Miller, D. Wentzla, F. Ghodrat, B. Greenwald, H. Ho, M. Lee, P. Johnson, W. Lee, A. Ma, A. Saraf, M. Seneski, N. Shnidman, V. Frank, S. Amarasinghe, and A. Agarwal, The RAW Microprocessor: A computational fabric for software circuits and general purpose programs, IEEE Micro, Vol. 2, No. 22, 2002.
  4. H. Singh, M.-H. Lee, G. Lu, F. J. Kurdahi, N. Bagherzadeh, and E. M. C. Filho, Morphosys: An integrated reconfigurable system for data-parallel and computation- intensive applications, IEEE Transactions on Computers, Vol. 49, No. 5, 2000.
  5. S. C. Goldstein, H. Schmit, M. Budiu, S. Cadambi, M. Moe, and R. R. Taylor, PipeRench: A reconfigurable architecture and compiler, IEEE Computer, Vol. 33, No. 4, 2000.
  6. C. Ebeling, D. Cronquist, and P. Franklin, RaPiDReconfigurable pipeline Datapath, Proceedings of International Workshop on Field Programmable Logic and Applications, 1996.
  7. PACT XPP Technologies, 2002-2014. http://www. pactxpp.com.
  8. H. Zhang, V. Prabhu, V. George, M. Wan, M. Benes, A. Abnous, and J. M. Rabaey, A 1V heterogeneous reconfigurable DSP IC for wireless baseband digital signal processing, IEEE Journal of Solid-State Circuits, Vol. 35, No. 11, 2000.
  9. Silicon Hive, 2004. http://silicon-hive.com.
  10. M. Jo, D. Lee, K. Han, and K. Choi, "Design of a coarsegrained reconfigurable architecture with floating-point support and comparative study," Integration, the VLSI Journal, Vol. 47, No. 2, 2014.
  11. F.-J. Veredas, M. Scheppler, W. Moffat, and B. Mei, Custom implementation of the coarse-grained recon figurable ADRES architecture for multimedia purposes, Proceedings of International Conference on Field Programmable Logic and Applications, 2005.
  12. N. R. Miniskar, P. S. Gode, S. Kohli, and D. Yoo, Function inlining and loop unrolling for loop acceleration in reconfigurable processors, Proceedings of International Conference on Compilers, Architectures and Synthesis for Embedded Systems, 2012.
  13. J. A. Fisher, P. Faraboschi, and C. Young, Embedded Computing: A VLIW Approach to Architecture, Compilers, and Tools, Morgan Kaufmann, 2005.
  14. B. R. Rau, Iterative modulo scheduling: an algorithm for software pipelining loops, Proceedings of International Symposium on Microarchitecture(MICRO), 1994.
  15. M. Ahn, D. Yoo, S. Ryu, and J. Kim, The acceleration of various multimedia applications on reconfigurable processor, Proceedings of IEEE International Conference on Consumer Electronics, 2013.
  16. S. Mahlke, D. Lin, W. Chen, R. Hank, and R. Bringmann, Effective compiler support for predicated execution using the hyperblock, Proceedings of International Symposium on Microarchitecture(MICRO), 1992.
  17. Khronos Group. http://www.khronos.org/opencl/.
  18. The LLVM Compiler Infrastructure. http://llvm.org/.
  19. H. Park, K. Fan, S. Mahlke, T. Oh, H. Kim, and H.-S. Kim, Edge-centric modulo scheduling for coarse-grained reconfigurable architectures. Proceedings of International Conference on Parallel Architectures and Compilation Techniques(PACT), 2008.
  20. T. Oh, B. Egger, H. Park, and S. Mahlke, Recurrence Cycle Aware Modulo Scheduling for Coarse-Grained Reconfigurable Architectures, Proceedings on Conference on Languages, Compilers, and Tools for Embedded Systems(LCTES), 2009.