정보과학회지 (Communications of the Korean Institute of Information Scientists and Engineers)

한국정보과학회 (Korean Institute of Information Scientists and Engineers)
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네트워크 온 칩 기반 매니코어 시스템에서의 매핑 및 라우팅 기법

  • 발행 : 2014.05.16
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초록

키워드

참고문헌

  1. International Technology Roadmap for Semiconductors. available: http://www.itrs.net/.
  2. J. Howard, S. Dighe, Y. Hoskote, S. Vangal, D. Finan, G. Ruhl, D. Jenkins, H. Wilson, N. Borkar, and G. Schrom, "A 48-core IA-32 message-passing processor with DVFS in 45nm CMOS," ISSCC Dig. Tech. Pap., 2010.
  3. Tilera, The TILE-GxTM processor family, 2009. http://www.tilera.com/products/processors.
  4. G. Chrysos and S. P. Engineer, "Intel xeon phi coprocessor( codename knights corner)," In Proc. HC, 2012.
  5. W. J. Dally and B. Towles, "Route packets, not wires: On-chip interconnection networks," In Proc. DAC, 2001.
  6. Adapteva, Epiphany, a many-core processor architecture with up to 4096 processors on-chip, 2012. http:// www.adapteva.com/products/epiphany-ip/epiphany-ar chitecture-ip/.
  7. J. S. Kim, M. B. Taylor, J. Miller, and D. Wentzlaff, "Energy characterization of a tiled architecture processor with on-chip networks," In Proc. ISLPED, 2003.
  8. J. Hu and R. Marculescu, "Energy-aware mapping for tile-based NoC architectures under performance constraints," In Proc. ASPDAC, 2003.
  9. C.-L. Chou and R. Marculescu, "Contention-aware application mapping for network-on-chip communication architectures,"In Proc. ICCD, 2008.
  10. C. Marcon, N. Calazans, F. Moraes, A. Susin, I. Reis, and F. Hessel, "Exploring NoC mapping strategies: An energy and timing aware technique," In Proc. DATE, 2005.
  11. J. Lee, M.-K. Chung, Y.-G. Cho, S. Ryu, J. H. Ahn, and K. Choi, "Mapping and scheduling of tasks and communications on many-Core SoC under local memory constraint," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., 32(11):1748-1761, 2013. https://doi.org/10.1109/TCAD.2013.2266405
  12. C.-L. Chou, U. Y. Ogras, and R. Marculescu, "Energyand performance-aware incremental mapping for networks on chip with multiple voltage levels," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., 27(10):1866-1879, 2008. https://doi.org/10.1109/TCAD.2008.2003301
  13. A. M. Amory, C. A. Marcon, F. G. Moraes, and M. S. Lubaszewski, "Task mapping on NoC-based MPSoCs with faulty tiles: Evaluating the energy consumption and the application execution time," In Proc. RSP, 2011.
  14. E. Carvalho and F. Moraes, "Congestion-aware task mapping in heterogeneous MPSoCs," In Proc. SOC, 2008.
  15. B. Sethuraman and R. Vemuri, "OptiMap: a tool for automated generation of NoC architectures using multiport routers for FPGAs," In Proc. DATE, 2006.
  16. S. Murali and G. De Micheli, "Bandwidth-constrained mapping of cores onto NoC architectures," In Proc. DATE, 2004.
  17. L. G. Valiant and G. J. Brebner, "Universal schemes for parallel communication," In Proc. STOC, 1981.
  18. A. Singh, Load-balanced routing in interconnection networks, Stanford University, 2005.
  19. J. Hu and R. Marculescu, "Exploiting the routing flexibility for energy/performance aware mapping of regular NoC architectures," In Proc. DATE, 2003.
  20. J. Lee, D. Lee, S. Kim, and K. Choi, "Deflection routing in 3D network-on-chip with limited vertical bandwidth," ACM Trans. Des. Autom. Electron. Syst., 18(4):50, 2013.
  21. A. Rahmani, K. Latif, K. R. Vaddina, P. Liljeberg, J. Plosila, and H. Tenhunen, "ARB-NET: A novel adaptive monitoring platform for stacked mesh 3D NoC architectures," In Proc. ASPDAC, 2012.
  22. M. D. Schroeder, A. D. Birrell, M. Burrows, H. Murray, R. M. Needham, T. L. Rodeheffer, E. H. Satterthwaite, and C. P. Thacker, "Autonet: A high-speed, self-configuring local area network using point-to-point links," IEEE J. Sel. Areas Commun., 9(8):1318-1335, 1991. https://doi.org/10.1109/49.105178