ETRI Journal

  • 제35권4호
  • /
  • Pages.638-643
  • /
  • 2013
  • /
  • 1225-6463(pISSN)
  • /
  • 2233-7326(eISSN)
한국전자통신연구원 (Electronics and Telecommunications Research Institute)
권호 표지
DOI QR코드

DOI QR Code

A Broadband Digital Step Attenuator with Low Phase Error and Low Insertion Loss in 0.18-${\mu}m$ SOI CMOS Technology

  • Cho, Moon-Kyu (Department of Electronic Engineering, Kwangwoon University) ;
  • Kim, Jeong-Geun (Department of Electronic Engineering, Kwangwoon University) ;
  • Baek, Donghyun (School of Electrical Engineering, Chung-Ang University)
  • 투고 : 2012.08.06
  • 심사 : 2013.01.11
  • 발행 : 2013.08.01
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

This paper presents a 5-bit digital step attenuator (DSA) using a commercial 0.18-${\mu}m$ silicon-on-insulator (SOI) process for the wideband phased array antenna. Both low insertion loss and low root mean square (RMS) phase error and amplitude error are achieved employing two attenuation topologies of the switched path attenuator and the switched T-type attenuator. The attenuation coverage of 31 dB with a least significant bit of 1 dB is achieved at DC to 20 GHz. The RMS phase error and amplitude error are less than $2.5^{\circ}$ and less than 0.5 dB, respectively. The measured insertion loss of the reference state is less than 5.5 dB at 10 GHz. The input return loss and output return loss are each less than 12 dB at DC to 20 GHz. The current consumption is nearly zero with a voltage supply of 1.8 V. The chip size is $0.93mm{\times}0.68mm$, including pads. To the best of the authors' knowledge, this is the first demonstration of a low phase error DC-to-20-GHz SOI DSA.

키워드

참고문헌

  1. B. Khabbaz, A. Pospishil, and H.P. Singh, "DC-to-20-GHz MMIC Multibit Digital Attenuators with On-Chip TTL Control," IEEE J. Solid-State Circuits, vol. 27, no. 10, Oct. 1992, pp. 1457-1462. https://doi.org/10.1109/4.156454
  2. D.W. Kang et al., "Single and Four-Element Ka-Band Transmit/Receive Phased-Array Silicon RFICs with 5-Bit Amplitude and Phase Control," IEEE Trans. Microw. Theory Tech., vol. 57, no. 12, Dec. 2009, pp. 3534-3543. https://doi.org/10.1109/TMTT.2009.2033302
  3. OMMIC, "CGY2171XBUH: 6-Bit 1-15 GHz Attenuator," datasheet, Limeil-Brevannes, France, Apr. 2010. Available: http://www.ommic.fr/produits/w2171b-39
  4. B.H. Ku and S.C. Hong, "6-Bit CMOS Digital Attenuators with Low Phase Variations for X-Band Phased-Array Systems," IEEE Trans. Microw. Theory Tech., vol. 58, no. 7, July 2010, pp. 1651-1663. https://doi.org/10.1109/TMTT.2010.2049691
  5. S. Walker, "A Low Phase Shift Attenuator," IEEE Trans. Microw. Theory Tech., vol. 42, no. 2, Feb. 1994, pp. 182-185. https://doi.org/10.1109/22.275244
  6. L. Sjogren et al., "A Low Phase-Error 44-GHz HEMT Attenuator," IEEE Microw. Wireless Compon. Lett., vol. 8, no. 5, May 1998, pp. 194-195.
  7. I.-K. Ju, Y.-S. Noh, and I.-B. Yom, "Ultra Broadband DC to 40 GHz 5-Bit pHEMT MMIC Digital Attenuator," Proc. Eur. Microw. Conf., Paris, France, Oct. 2005, pp. 995-998.
  8. H. Dogan, R.G. Meyer, and A.M. Niknejad, "Analysis and Design of RF CMOS Attenuators," IEEE J. Solid-State Circuits, vol. 43, no. 10, Oct. 2008, pp. 2269-2283. https://doi.org/10.1109/JSSC.2008.2004325
  9. M. Parlak and J.F. Buckwalter, "A 2.5-dB Insertion Loss, DC-60 GHz CMOS SPDT Switch in 45-nm SOI," Proc. IEEE Compound Semicond. Integr. Circuits Symp. Dig., Oct. 2011, pp. 1-4.
  10. J.H. Jeong et al., "High Power Digitally-Controlled SOI CMOS Attenuator with Wide Attenuation Range," IEEE Microw. Wireless Compon. Lett., vol. 21, no. 8, Aug. 2011, pp. 433-435. https://doi.org/10.1109/LMWC.2011.2160160
  11. M. Granger-Jones, B. Nelson, and E. Franzwa, "A Broadband High Dynamic Range Voltage Controlled Attenuator MMIC with IIP3 > +47dBm over Entire 30dB Analog Control Range," IEEE MTT-S Int. Microw. Symp. Dig., June 2011, pp. 1-4.

피인용 문헌

  1. CMOS transceiver with high input dynamic range and wide modulation-depth for RFID and NFC readers vol.85, pp.2, 2013, https://doi.org/10.1007/s10470-015-0612-1