Journal of the Institute of Electronics and Information Engineers (전자공학회논문지)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Design of a Current Steering 10-bit CMOS D/A Converter Based on a Self-Calibration Bias Technique

자가보정 바이어스 기법을 이용한 Current Steering 10-bit CMOS D/A 변환기 설계

  • Lim, ChaeYeol (Department of Semiconductor Science, Dongguk University) ;
  • Lee, JangWoo (Department of Semiconductor Science, Dongguk University) ;
  • Song, MinKyu (Department of Semiconductor Science, Dongguk University)
  • 임채열 (동국대학교 반도체과학과) ;
  • 이장우 (동국대학교 반도체과학과) ;
  • 송민규 (동국대학교 반도체과학과)
  • Received : 2013.04.15
  • Published : 2013.10.25
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Abstract

In this paper, a current steering 10-bit CMOS D/A converter to drive a NTSC/PAL analog TV is proposed. The proposed D/A converter has a 50MS/s operating speed with a 6+4 segmented type. Further, in order to minimize the device mismatch, a self-calibration bias technique with a fully integrated termination resistance is discussed. The chip has been fabricated with a 3.3V 0.11um 1-poly 6-metal CMOS technology. The effective chip area is $0.35mm^2$ and power consumption is about 88mW. The experimental result of SFDR is 63.1dB, when the input frequency is 1MHz at the 50MHz of sampling frequency.

본 논문에서는 NTSC/PAL 아날로그 TV를 구동하기 위한 10-bit current steering D/A 변환기를 제안하였다. 제안하는 D/A 변환기는 50MS/s 의 동작속도를 가지며, 6+4 분할 구조로 설계되었다. 또한 새로운 개념의 자가보정 바이어스 기법을 적용하여 칩 내부의 종단저항을 사용하고도 공정오차를 최소화 하였다. 제안하는 D/A 변환기는 3.3V 0.11um 1-poly 6-metal CMOS 공정을 사용하여 제작되었다. 제작된 칩의 유효 면적은 $0.35mm^2$, 3.3V 전원전압 상에서 약 88mW의 전력소모를 나타내었다. 실험 결과는 변환 속도 50MS/s, 입력 주파수 1MHz에서 SFDR 63.1dB의 특성을 나타내었다.

Keywords

References

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