Journal of the Institute of Electronics and Information Engineers (전자공학회논문지)

The Institute of Electronics and Information Engineers (대한전자공학회)
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High-Performance Low-Complexity Iterative BCH Decoder Architecture for 100 Gb/s Optical Communications

100 Gb/s급 광통신시스템을 위한 고성능 저면적 반복 BCH 복호기 구조

  • Yang, Seung-Jun (Department of Information and Communication Engineering, Inha University) ;
  • Yeon, Jaewoong (Department of Information and Communication Engineering, Inha University) ;
  • Lee, Hanho (Department of Information and Communication Engineering, Inha University)
  • 양승준 (인하대학교 정보통신공학과) ;
  • 연제웅 (인하대학교 정보통신공학과) ;
  • 이한호 (인하대학교 정보통신공학과)
  • Received : 2012.11.28
  • Published : 2013.07.25
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Abstract

This paper presents a iterative Bose-Chaudhuri-hocquenghem (i-BCH) code and its high-speed decoder architecture for 100 Gb/s optical communications. The proposed architecture features a very high data processing rate as well as excellent error correction capability. The proposed 6-iteration i-BCH code structure with interleaving method allows the decoder to achieve 9.34 dB net coding gain performance at $10^{-15}$ decoder output bit error rate to compensate for serious transmission quality degradation. The proposed high-speed i-BCH decoder architecture is synthesized using a 90-nm CMOS technology. It can operate at a clock frequency of 430 MHz and achieve a data processing rate of 100 Gb/s. Thus, it has potential applications in next generation forward error correction (FEC) schemes for 100 Gb/s optical communications.

본 논문은 100 Gb/s급 광통신 시스템을 위한 반복적인 Bose-Chaudhuri-Hocquenghem (BCH) 부호와 고성능 복호기 구조를 보여준다. 제안된 구조는 고속 데이터 처리율뿐만 아니라 뛰어난 오류정정능력을 보여준다. 제안된 6회 반복 i-BCH 복호기는 메모리 기반의 인터리브 기술을 이용하였으며 6번의 반복 복호시 $10^{-15}$ post-FEC Bit Error Rate(BER) 기준 9.34 dB의 강력한 Net Coding Gain(NCG) 성능을 제공한다. 제안된 고성능 i-BCH 복호기의 구조는 90-nm CMOS 공정을 사용하여 합성한 후 수행한 성능 분석 결과 430 MHz의 동작 속도와 100 Gb/s의 데이터 처리율을 갖는다. 따라서 100 Gb/s급 광통신시스템을 위한 차세대 순방향 오류정정 구조에 적용할 수 있다.

Keywords

References

  1. 최창석, 이한호, "100Gb/s급 광통신시스템을 위한 3-병렬 Reed-Solomon 기반 FEC 구조 설계," 전자공학회 논문지, 제46권 SD편 제 11호, pp. 48-55, 2009년 11월.
  2. Forward Error Correction for high bit-rate DWDM Submarine Systems," Telecommunication Standardization Section, International Telecom. Union, ITU-T Recommendation G.975.1, Dec. 2004.
  3. K. Onohara et. al, "Soft-decision-based Forward Error Correction for 100 Gb/s Transport Systems," IEEE Jour. of Selected Topics in Quantum Electronics, vol. 16, pp. 1258-1267, Sept. 2010. https://doi.org/10.1109/JSTQE.2010.2040809
  4. 이만영, "BCH 부호와 Reed-Solomon 부호," 민음사, 1990.
  5. H. Hsu, S. Wang and A. Wu, "A Novel Low-Cost Multi-Mode Reed Solomon Decoder Design Based on Peterson-Gorenstein-Zierler Algorithm," Journal of VLSI Signal Processing, vol. 34, no. 3, pp. 251-259, Nov. 2003. https://doi.org/10.1023/A:1023200419497
  6. M. Srinivasan and D. V. Sarwate, "Malfunction in the Peterson-Gorenstein-Zierler decoder," IEEE Trans. on Information Theory, vol. 11, no. 4, pp. 580-585, Oct. 1965. https://doi.org/10.1109/TIT.1965.1053833
  7. J. L. Massey, "Step-by-step decoding of the Bose-Chaudhuri-Hoquenhe m codes," IEEE Trans. Inform. Theory, vol. IT-6, pp. 580-585, Oct. 1965.
  8. D. V. Sarwate and N. R. Shanbhag, "High-speed Architectures for Reed-Solomon decoders," IEEE Transactions on VLSI Systems, vol. 9, pp. 641-655, Oct. 2001. https://doi.org/10.1109/92.953498
  9. S. Lee and H. Lee, "A High-Speed Pipelined Degree Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders," IEICE Trans. on Fundamentals of Electronics, Communications, and Computer Sciences, vol. E91-A, no. 3, pp. 830-835, Mar. 2008. https://doi.org/10.1093/ietfec/e91-a.3.830
  10. E. R. Berlekamp, "Algebraic Coding Theory," New York: McGraw-Hill, 1968. (revised ed. - Laguna Hills, CA: Aegean Park, 1984).
  11. H. Kristian, H. Wahyono, K. Rizki, T. Adiono,"Ultra-fast-scalable BCH decoder with efficient-Extended Fast Chien Search,"IEEE International Conference on Computer Science and Information Technology (ICCSIT), pp. 338-343, July 2010.
  12. S. Yoon, H. Lee and K. Lee, "High-speed two-parallel concatenated BCH-based super-FEC architecture for optical communications," IEICE Trans. Fundamentals, vol.E93-A, no.4, pp.769-777, April 2010. https://doi.org/10.1587/transfun.E93.A.769
  13. K. Lee, H.-G. Kang, J.-I. Park and H. Lee, "A high-speed low-complexity concatenated BCH decoder architecture for 100Gb/s Optical communications," Journal of Signal Processing Systems, vol. 6, no. 1, pp. 43-55, Jan. 2012.
  14. K. Lee and H. Lee, "A High-Performance Concatenated BCH Code and Its Hardware Architecture for 100 Gb/s Long-haul Optical Communications," International SoC Design Conference (ISOCC2010), pp. 428-431, Nov. 2010.

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