References
- R. Scott List, C. Webb, and S. E. Kim, "3D wafer stacking technology", Proc. AMC, 18, 29-36 (2002).
- P. Morrow, M. Kobrinsky, M. Harmes, C. Park, S. Ramanathan, V. Ramachandrarao, H. Park, G. Kloster, S. List, and S. E. Kim, "Wafer level 3D interconnect in Cu bonding", Proc. AMC, 20, 125-130 (2004).
- R. Plieninger, M. Dittes, and K. Pressel, "Modern IC packaging trends and their reliability implications", Microelectron. Reliab., 46, 1868-1873 (2006). https://doi.org/10.1016/j.microrel.2006.08.008
- M. Lai, S. Li, J. Shih, and K. Chen, "Wafer-level three-dimensional integrated circuits (3D IC): Schemes"s, Microelectron. Eng., 88, 3282-3286 (2011). https://doi.org/10.1016/j.mee.2011.05.036
- Y. Kim, S. K. Kang, S. Kim, and S. E. Kim, "Wafer warpage analysis of stacked wafers for 3D integration", Microelectron. Eng., 89, 46-49 (2012). https://doi.org/10.1016/j.mee.2011.01.079
- S. G. Kang, J. Lee, E. S. Kim, N. Lim, S. H. Kim, S. Kim and S. E. Kim, "Fabrication and challenges of Cu-to-Cu wafer bonding", J. Microelectron. Packag. Soc., 19(2), 29-33 (2012). https://doi.org/10.6117/kmeps.2012.19.2.029
- R. Patti, "Three-dimensional integrated circuits and the future of system-on-chip designs", Proc. the IEEE, 94(6), 1214-1224 (2006). https://doi.org/10.1109/JPROC.2006.873612
- M. K. Choi and E. Kim, "Effect of Si wafer ultra-thinning on the silicon surface for 3D integration", J. Microelectron. Packag. Soc., 15(2), 133-137 (2008).
- J. Q. Lu, "3-D hyperintegration and packaging technologies for micron-nano systems", Proc. the IEEE, 97(1), 18-30 (2009). https://doi.org/10.1109/JPROC.2008.2007458
- M. Taouil and S. Hamdioui, "Yield improvement for 3D wafer-to-wafer stacked memories", J. Electron. Test., 28(4), 523-534 (2012). https://doi.org/10.1007/s10836-012-5314-3
- M. Taouil, S. Hamdioui, J. Verbree, and E. J. Marinissen, "On maximizing the compound yield for 3D wafer-to-wafer stacked ICs", IEEE ITC, 1-10 (2010).
- L. Smith, G. Smith, S. Hosali, and S. Arkalgud, "Yield considerations in the choice of 3D technology", IEEE ISSM, 535-537 (2007).
- S. Reda, G. Smith, and L. Smith, "Maximizing the functional yield of wafer-to-wafer 3-D integration", IEEE Trans. VLSI System, 17(9), 1357-1362 (2009). https://doi.org/10.1109/TVLSI.2008.2003513
- E. Singh, "Exploiting rotational symmetries for improved stacked yields in W2W 3D-SICs", IEEE VTS, 32-37 (2011).
- C. Chou, Y. Huang, and J. Li, "Yield-enhancement techniques for 3D random access memories", IEEE VLSI-DAT, 104-107 (2010).
- M. Taouil and S. Hamdioui, "Layer redundancy based yield improvement for 3D wafer-to-wafer stacked memories", IEEE ETS, 54-50 (2011).
- B. Vaidyanathan, Y. Wang, and Y. Xie, "Cost-aware lifetime yield analysis of heterogeneous 3D on-chip cache", IEEE Int. MTDT, 65-70 (2009).
- S. K. Lu, T. W. Chang, and H. Y. Hsu, "Yield enhancement techniques for 3-dimensional random access memories", Microelectron. Reliab., 52, 1065-1070 (2012). https://doi.org/10.1016/j.microrel.2011.12.017
- Y. Zhao, S. Khursheed, and B. M. Al-Hashimi, "Cost-effective TSV grouping for yield improvement of 3D-ICs", IEEE ATS, 201-206 (2011).
- J. H. Lau, "TSV manufacturing yield and hidden costs for 3D IC integration", IEEE ECTC, 1031-1042 (2010).
- S. Hamdioui and M. Taouil, "Yield improvement and test cost optimization for 3D stacked ICs", IEEE ATS, 480-485 (2011).
- E. Kim and J. Sung, "Yield challenges in wafer stacking technology", Microelectron. Reliab., 48, 1102-1105 (2008). https://doi.org/10.1016/j.microrel.2008.03.010
- M. Kawano, S. Uchiyama, Y. Egawa, N. Takahashi, Y. Kurita, K. Soejima, M. Komuro, S. Matsui, K. Shibata, J. Yamada, M. Ishino, H. Ikeda, Y. Saeki, O. Kato, H. Kikuchi and T. Mitsuhashi, "A 3D packaging technology for 4 Gbit stacked DRAM with 3 Gbps data transfer", IEEE IEDM, 1-4 (2006).
- X. Wu, G. Sun, Guangyu, X. Dong, R. Das, Y. Xie, Yuan, C. Das, and J. Li, "Cost-driven 3D integration with interconnect layers", 47th IEEE DAC, 150-155 (2010).
- X. Dong and Y. Xie, "System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs)", IEEE ASP-DAC, 234-241 (2009).