Journal of Computing Science and Engineering

  • 제7권1호
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  • Pages.53-66
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  • 2013
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  • 1976-4677(pISSN)
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  • 2093-8020(eISSN)
한국정보과학회 (Korean Institute of Information Scientists and Engineers)
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Bounding Worst-Case DRAM Performance on Multicore Processors

  • Ding, Yiqiang (Department of Electrical and Computer Engineering, Virginia Commonwealth University) ;
  • Wu, Lan (Department of Electrical and Computer Engineering, Virginia Commonwealth University) ;
  • Zhang, Wei (Department of Electrical and Computer Engineering, Virginia Commonwealth University)
  • 투고 : 2013.02.12
  • 심사 : 2013.03.01
  • 발행 : 2013.03.30
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초록

Bounding the worst-case DRAM performance for a real-time application is a challenging problem that is critical for computing worst-case execution time (WCET), especially for multicore processors, where the DRAM memory is usually shared by all of the cores. Typically, DRAM commands from consecutive DRAM accesses can be pipelined on DRAM devices according to the spatial locality of the data fetched by them. By considering the effect of DRAM command pipelining, we propose a basic approach to bounding the worst-case DRAM performance. An enhanced approach is proposed to reduce the overestimation from the invalid DRAM access sequences by checking the timing order of the co-running applications on a dual-core processor. Compared with the conservative approach, which assumes that no DRAM command pipelining exists, our experimental results show that the basic approach can bound the WCET more tightly, by 15.73% on average. The experimental results also indicate that the enhanced approach can further improve the tightness of WCET by 4.23% on average as compared to the basic approach.

키워드

참고문헌

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피인용 문헌

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