Journal of Electrical Engineering and Technology

  • 제8권2호
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  • Pages.316-325
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  • 2013
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  • 1975-0102(pISSN)
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  • 2093-7423(eISSN)
대한전기학회 (The Korean Institute of Electrical Engineers)
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Asymmetric Cascaded Multi-level Inverter: A Solution to Obtain High Number of Voltage Levels

  • Banaei, M.R. (Electrical Engineering Department, Faculty of Engineering, Azarbaijan Shahid Madani University) ;
  • Salary, E. (Electrical Engineering Department, Faculty of Engineering, Azarbaijan Shahid Madani University)
  • 투고 : 2012.03.19
  • 심사 : 2012.09.20
  • 발행 : 2013.03.01
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⟨ 이전 논문 다음 논문 ⟩

초록

Multilevel inverters produce a staircase output voltage from DC voltage sources. Requiring great number of semiconductor switches is main disadvantage of multilevel inverters. The multilevel inverters can be divided in two groups: symmetric and asymmetric converters. The asymmetric multilevel inverters provide a large number of output steps without increasing the number of DC voltage sources and components. In this paper, a novel topology for multilevel converters is proposed using cascaded sub-multilevel Cells. This sub-multilevel converters can produce five levels of voltage. Four algorithms for determining the DC voltage sources magnitudes have been presented. Finally, in order to verify the theoretical issues, simulation is presented.

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참고문헌

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