References
- M. S. Bakir, B. Dang and J. D. Meindl, "Revolutionary Nanosilicon Ancillary Technologies for Ultimate-Performance Gigascale Systems", Proc. IEEE CICC, San Jose, 421, IEEE SSCS/EDS (2007).
- G. G. Shahidi, "Evolution of CMOS Technology at 32 nm and Beyond", Proc. IEEE CICC, San Jose, 413, IEEE SSCS/EDS (2007).
- J. W. Joyner, P. Zarkesh-Ha and J. D. Meindl, "Global Interconnect Design in a Three-Dimensional System-on-a-Chip", IEEE Tran. VLSI Systems, 12, 367 (2004). https://doi.org/10.1109/TVLSI.2004.825835
- R. S. List, C. Webb and S. E. Kim, "3D Wafer Stacking Technology", Proc. AMC, 18, 29 (2002).
- J. Balachandran, S. Brebels, G. Carchon, M. Kuijk, W. De Raedt, B. Nauwelaers and E. Beyne, "Wafer-Level Package Interconnect Options", IEEE VLSI Systems, 14(6), 654 (2006). https://doi.org/10.1109/TVLSI.2006.878229
- E. Kim, "Overview of High Performance 3D-WLP", Kor. J. Mater. Res., 17(7), 371 (2007). https://doi.org/10.3740/MRSK.2007.17.7.347
- E. Kim and J. Sung, "Yield Challenges in Wafer Stacking Technology", Microelectron. Reliab., 48, 1102 (2008). https://doi.org/10.1016/j.microrel.2008.03.010
- Y. Kim, S. Kang, S. Kim and S. E. Kim, "Wafer Warpage Analysis of Stacked Wafers for 3D Integration", Microelectron. Eng., 89, 46 (2012). https://doi.org/10.1016/j.mee.2011.01.079
- G. Huang, M. Bakir, A. Naeemi, H. Chen and J. D. Meindl, "Power Delivery for 3D Chip Stacks: Physical Modeling and Design Implication", IEEE EPEPS, 205 (2007).
- G. Y. Tang, S. P. Tan, N. Khan, D. Pinjala, J. H. Lau, A. B. Yu, K. Vaidyanathan and K. C. Toh "Integrated Liquid Cooling Systems for 3-D Stacked TSV Modules", IEEE Trans. Compon. Packag. Technol., 33(1), 184 (2010). https://doi.org/10.1109/TCAPT.2009.2033039
- http://www.itrs.net
- A. J. McNamara, Y. Joshi and Z. M. Zhang, "Characterization of Nanostructured Thermal Interface Materials: A Review", Int. J. Therm. Sci., 62, 2 (2011).
- Jun Xu and T. S. Fisher, "Enhancement of Thermal Interface Materials with Carbon Nanotube Arrays", Int. J. Heat Mass Transfer, 49(9-10), 1658 (2006). https://doi.org/10.1016/j.ijheatmasstransfer.2005.09.039
- A. Hamdan, A. McLanahan, R. Richards and C. Richards, "Characterization of a Liquid-Metal Microdroplet Thermal Interface Material", Exp. Therm. Fluid Sci., 35(7), 1250 (2011). https://doi.org/10.1016/j.expthermflusci.2011.04.012
- S. N. Paisner, "Nanotechnology and Mathematical Methods for High-Performance Thermal Interface Materials", Global SMT & Packag., 36 (2008).
- J. Darabi and K. Ekula, "Development of a Chip-Integrated Micro Cooling Device", Microelectron. J., 34(11), 1067 (2003). https://doi.org/10.1016/j.mejo.2003.09.010
- Y. M. Hung and Q. Seng, "Effects of Geometric Design on Thermal Performance of Star-Groove Micro-Heat Pipes", Int. J. Heat Mass Transfer, 54(5-6), 1198 (2011). https://doi.org/10.1016/j.ijheatmasstransfer.2010.09.070
- J. Vaes, W. Dehaene, E. Beyne and Y. Travaly, "Integration Challenges of Copper Through Silicon Via (TSV) Metallization for 3D-Stacked IC Integration", Microelectron. Eng., 88(50), 745 (2011). https://doi.org/10.1016/j.mee.2010.06.026
- R. Hon, S. W. Ricky Lee, S. X. Zhang and C. K. Wong, "Multi-Stack Flip Chip 3D Packaging with Copper Plated Through-Silicon Vertical Interconnection", IEEE EPTC, 384 (2005).
- G. Upadhya, M. Munch, P. Zhou, J. Hom, D. Werner and M. McMaster, "Micro-Scale Liquid Cooling System for High Heat Flux Processor Cooling Applications", IEEE STMMS,, 116 (2006).
- S. C. Mohapatra and D. Loikits, "Advances in Liquid Coolant Technologies for Electronics Cooling", IEEE STMMS, 354 (2005).
- Y. Wei and Y. Joshi, "Stacked Microchannel Heat Sinks for Liquid Cooling of Microelectronic Components", ASME J. Electron. Packag., 126, 60 (2004). https://doi.org/10.1115/1.1647124
- H. Oprins, G. Van der Veken, C. C. S. Nicole, C. J. M. Lasance and M. Baelmans, "On-chip Liquid Cooling with Integrated Pump Technology", IEEE Trans. Compon. Packag. Technol., 30(2), 209 (2007). https://doi.org/10.1109/TCAPT.2007.898301
- H. Y. Zhang, D. Pinjila, T. N. Wong and Y. K. Joshi, "Development of Liquid Cooling Techniques for Flip Chip Ball Grid Array Packages with High Flux Heat Dissipations", IEEE Trans. Compon. Packag. Technol., 28(1), 127 (2005). https://doi.org/10.1109/TCAPT.2004.843164
- P. S. Lee, J. C. Ho and H. Xue, "Experimental Study on Laminar Heat Transfer in Microchannel Heat Sink", IEEE ITHERM, 379 (2002).
- J. Li and G. P. Peterson, "Geometric Optimization of a Micro Heat Sink with Liquid Flow", IEEE Trans. Compon. Packag. Technol., 29(1), 145 (2006). https://doi.org/10.1109/TCAPT.2005.853170
- T. Chen and S. V. Garimella, "Flow Boiling Heat Transfer to a Dielectric Coolant in a Microchannel Heat Sink", IEEE Trans. Compon. Packag. Technol., 30(1), 24 (2007). https://doi.org/10.1109/TCAPT.2007.892063
- J. Lee and I. Mudawar, "Low-Temperature Two-Phase Microchannel Cooling for High-Heat-Flux Thermal Management of Defense Electronics", IEEE Trans. Compon. Packag. Technol., 32(2), 453 (2009). https://doi.org/10.1109/TCAPT.2008.2005783
- T. Brunschwiler, B. Michel, H. Rothuizen, U. Kloter, B. Wunderle. H. Oppermann and H. ReichlKloter, "Interlayer Cooling Potential in Vertically Integrated Packages", Microsystem Tech., 15, 57 (2009). https://doi.org/10.1007/s00542-008-0690-4
- Y. Zhang, C. King, J. Zaveri, Y. J. Kim, V. Sahu, Y. Joshi and M. Bakir, "Coupled Electrical and Thermal 3D IC Centric Microfluidic Heat Sink Design and Technology", Proc. 61th ECTC, Lake Buena Vista, 2037, IEEE CPMT (2011).
- B. Dang, M. S. Bakir and J. D. Meindl, "Integrated Thermal- Fluidic I/O Interconnects for an On-Chip Microchannel Heat Sink", IEEE EDL, 27, 117 (2006). https://doi.org/10.1109/LED.2005.862693
- M. Bakir, C. King, D. Sekar, H. Thacker, B. Dang, G. Huang, A. Naeemi and J. D. Meindl, "3D Heterogeneous Integrated Systems: Liquid Cooling, Power Delivery, and Implementation", Proc. IEEE CICC, San jose, 663, IEEE SSCS/EDS (2008).
- D. Sekar, C.King, B. Dang, T. Spencer, H. Thacker, P. Joseph, M. Bakir and J. Meind "A 3D-IC Technology with Integrated Microchannel Cooling", IEEE IITC, 13 (2008).
- N. Khan, L. H. Yu, T. S. Pin, S. W. Ho, V. Kripesh, D. Pinjala J. H. Lau and T. K. Chuan "3-D Packaging With Through- Silicon Via (TSV) for Electrical and Fluidic Interconnections", IEEE Trans. Comp., Packag., Manuf. Technol., 3(2), 221 (2013). https://doi.org/10.1109/TCPMT.2012.2186297
- A. Yu, N. Khan, G. Archit, D. Pinjala, K. C. Toh, V. Kripesh, S. W. Yoon and J. Lau, "Fabrication of Silicon Carriers with TSV Electrical Interconnections and Embedded Thermal Solutions for High Power 3-D Package", Proc. 58th ECTC, Lake Buena Vista, 24, IEEE CPMT (2008).
- J. H. Lau and T. G. Yue, "Effects of TSVs (Through-Silicon Vias) on Thermal Performances of 3D IC Integration System- In-Package (SiP)", Microelectron. Reliab., 52, 2660 (2012). https://doi.org/10.1016/j.microrel.2012.04.002
- T. G. Yue, T. S. Pin, N. Khan, D. Pinjala, J. H. Lau, Y. A. Bin, K. Vaidyanathan and T. K. Chuan, "Fluidic Interconnects in Integrated Liquid Cooling Systems for 3-D Stacked TSV Modules", Proc. 10th EPTC, Singapore, 552, IEEE Reliability/ CPMT/ED (2008).
- H. Mizunuma, C. Yang and Y. Lu, "Thermal Modeling for 3D-ICs with Integrated Microchannel Cooling", IEEE ICCAD, 256 (2009).
- B. Shi, A. Srivastava and A. Bar-Cohen, "Hybrid 3D-IC Cooling System Using Micro-fluidic Cooling and Thermal TSVs", IEEE ISVLSI, 33 (2012).
- D. Kearney, T. Hilt and P. Pham, "A Liquid Cooling Solution for Temperature Redistribution in 3D IC Architectures", Microelectron. J., 43(9), 602 (2012). https://doi.org/10.1016/j.mejo.2011.03.012
Cited by
- Cu Through-Via Formation using Open Via-hole Filling with Electrodeposition vol.21, pp.4, 2014, https://doi.org/10.6117/kmeps.2014.21.4.117
- Thermal Conductivity Measurement Method for the Thin Epoxy Adhesive Joint Layer vol.39, pp.4, 2021, https://doi.org/10.5781/jwj.2021.39.4.8