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Electronics and Telecommunications Research Institute (한국전자통신연구원)
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Fast NAND Flash Memory System for Instruction Code Execution

  • Jung, Bo-Sung (School of Electrical and Electronic Engineering, ERI, Gyeongsang National University) ;
  • Kim, Cheong-Ghil (Department of Computer Science, Namseoul University) ;
  • Lee, Jung-Hoon (School of Electrical and Electronic Engineering, ERI, Gyeongsang National University)
  • Received : 2011.11.09
  • Accepted : 2012.07.09
  • Published : 2012.10.31
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Abstract

The objective of this research is to design a high-performance NAND flash memory system containing a buffer system. The proposed instruction buffer in the NAND flash memory consists of two parts, that is, a fully associative temporal buffer for temporal locality and a fully associative spatial buffer for spatial locality. A spatial buffer with a large fetching size turns out to be effective for serial instructions, and a temporal buffer with a small fetching size is devised for branch instructions. Simulation shows that the average memory access time of the proposed system is better than that of other buffer systems with four times more space. The average miss ratio is improved by about 70% compared with that of other buffer systems.

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References

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Cited by

  1. High Performance NAND Flash Memory System with a Data Buffer vol.ea96, pp.12, 2012, https://doi.org/10.1587/transfun.e96.a.2645