Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

An Efficient Programmable Memory BIST for Dual-Port Memories

이중 포트 메모리를 위한 효율적인 프로그램 가능한 메모리 BIST

  • Park, Young-Kyu (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Han, Tae-Woo (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Kang, Sung-Ho (Department of Electrical and Electronic Engineering, Yonsei University)
  • 박영규 (연세대학교 전기전자공학과) ;
  • 한태우 (연세대학교 전기전자공학과) ;
  • 강성호 (연세대학교 전기전자공학과)
  • Received : 2012.04.18
  • Accepted : 2012.07.05
  • Published : 2012.08.25
Download PDF
⟨ Previous Next ⟩

Abstract

The development of memory design and process technology enabled the production of high density memory. As the weight of embedded memory within aggregate Systems-On-Chips(SoC) gradually increases to 80-90% of the number of total transistors, the importance of testing embedded dual-port memories in SoC increases. This paper proposes a new micro-code based programmable memory Built-In Self-Test(PMBIST) architecture for dual-port memories that support test various test algorithms. In addition, various test algorithms including March based algorithms and dual-port memory test algorithms are efficiently programmed through the proposed algorithm instruction set. This PMBIST has an optimized hardware overhead, since test algorithm can be implemented with the minimum bits by the optimized algorithm instructions.

메모리 설계 기술과 공정 기술의 발달은 고집적 메모리의 생산을 가능하게 하였다. 전체 Systems-On-Chips(SoC)에서 내장 메모리가 차지하는 비중은 점점 증가하여 전체 트랜지스터 수의 80%~90%를 차지하고 있어, SoC에서 내장된 이중 포트 메모리에 대한 테스트 중요성이 점점 증가하고 있다. 본 논문에서는 이중 포트 메모리를 위한 다양한 테스트 알고리즘을 지원하는 새로운 micro-code 기반의 programmable memory Built-In Self-Test(PMBIST) 구조를 제안한다. 또한 제안하는 알고리즘 명령어 구조는 March 기반 알고리즘과 이중 포트 메모리 테스트 알고리즘 등의 다양한 알고리즘을 효과적으로 구현한다. PMBIST는 테스트 알고리즘을 최적화된 알고리즘 명령어를 사용하여 최소의 bit으로 구현할 수 있어 최적의 하드웨어 오버헤드를 가진다.

Keywords

References

  1. S. Hamdioui, Z. Al-Ars, and A. J. Van de Goor, "Testing static and dynamic faults in random access memories," Proceeding of VLSI Test Symposium, pp. 395-400, Apr. 2002.
  2. S. Boutobza, M. Nicolaidis, K.M. Lamara, and A. Costa, "Programmable Memory BIST," Proceeding of IEEE International Test Conference, Paper 45.2, Nov. 2005.
  3. Yamasaki, I. Suzuki, A. Kobayashi, K. Horie, Y. Kobayashi, H. Aoki, H. Hayashi, K. Tada, K. Tsutsumida, and K. Higeta, "External memory BIST for system-in-package," Proceeding of International Test Conference, pp. 1145-1154, Nov. 2005.
  4. A. W. Hakmi, H. J. Wunderlich, C. G. Zoellin, A. Glowatz, F. Hapke, J. Schloeffel, and L. Souef, "Programmable deterministic Built-In Self-Test," Proceeding of IEEE International Test Conference, pp. 1-9, Oct. 2007.
  5. S. Hamdioui, A. J. Van de Goor, and M. Rodgers, "March SS: a test for all static simple RAM faults," Proceedings of IEEE International Workshop on Memory Technology, Design and Testing, pp. 95-100, Jul. 2002.
  6. S. Hamdioui, and A. J. Van de Goor, "Efficient tests for realistic faults in dual-port SRAMs," IEEE Transactions on Computers, vol. 51, No. 5, pp.460-473, 2002. https://doi.org/10.1109/TC.2002.1004586
  7. Y. Park, M. Yang, Y. Kim, D. Lee, and S. Kang, "An Efficiency Testing Algorithm for Realistic Faults in Dual-Port Memories," Journal of the Institute of Electrical Engineers of Korea, vol.43-SD, No. 2, pp.72-85, 2007.
  8. X. Du, N. Mukherjee, C. Hill, W-T. Cheng, and S. Reddy, "A Field Programmable Memory BIST Architecture Supporting Algorithms with Multiple Nested Loops," Proceeding of IEEE Asian Test Symposium, pp. 287-292, Nov. 2006.
  9. Y. Park, J. Park, T. Han, and S. Kang, "An Effective Programmable Memory BIST for Embedded Memory," IEICE Transactions on Information and Systems, vol. E92-D, no. 12, pp. 2508-2511,Dec. 2009. https://doi.org/10.1587/transinf.E92.D.2508
  10. A. Benso, S. Di Carlo, G. Di Natale, P. Prinetto, and M. Lobetti Bodoni, "A programmable BIST architecture for clusters of multiple-port SRAMs," Proceeding of IEEE International Test Conference, pp. 557-566, Oct. 2000.