JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Bus Data Compression Method on a Phase-Based On-Chip Bus

  • Received : 2011.07.24
  • Published : 2012.06.30
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Abstract

This paper provides a method for compression transmission of on-chip bus data. As the data traffic on on-chip buses is rapidly increasing with enlarged video resolutions, many video processor chips suffer from a lack of bus bandwidth and their IP cores have to wait for a longer time to get a bus grant. In multimedia data such as images and video, the adjacent data signals very often have little or no difference between them. Taking advantage of this point, this paper develops a simple bus data compression method to improve the chip performance and presents its hardware implementation. The method is applied to a Video Codec - 1 (VC-1) decoder chip and reduces the processing time of one macro-block by 13.6% and 10.3% for SD and HD videos, respectively

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References

  1. P. E. Landman, and J. M. Rabaey, "Architectural Power Analysis: The Dual Bit Type Method," IEEE Trans. VLSI Syst., Vol.3, No.2, pp.173-187, June, 1995. https://doi.org/10.1109/92.386219
  2. Y. Jin, Y. Lee, and H.-J. Lee, "A New Frame Memory Compression Algorithm with DPCM and VLC in a 4${\times}$4 Block," EURASIP Journal on Advances in Signal Processing, Vol.2009, Article ID 629285, 18 pages, Feb., 2010.
  3. T. Y. Lee, "A new frame-recompression algorithm and its hardware design for MPEG-2 video decoders," IEEE Trans. Circuits Syst. for Video Technology, Vol.13, No.6, pp.529-534, June, 2003. https://doi.org/10.1109/TCSVT.2003.813425
  4. Y. V. Ivanov and D. Moloney, "Reference frame compression using embedded reconstruction patterns for H.264/AVC decoders," in Proceedings of the 3rd International Conference on Digital Telecommunications (ICDT '08), Bucharest, Romania, July, 2008.
  5. J. Lee and H.-J. Lee, "Wire Optimization for Multimedia SoC and SiP Designs," IEEE Trans. Circuits Syst. I, Vol.55, No.8, pp.2202-2215, Sept., 2008. https://doi.org/10.1109/TCSI.2008.920153
  6. J.-H. Kim, "A Hybrid Pipelined Implementation of a Standard Video Decoder with an Aggressive MC Data Reuse," M. S. Thesis, Seoul National University, Seoul, Korea, 2007.
  7. M. R. Stan and W. P. Burleson, "Bus-invert coding for low power I/O," IEEE Trans. VLSI Syst., Vol.3, pp.49-58, Mar., 1995. https://doi.org/10.1109/92.365453
  8. P. Panda and N. Dutt, "Reducing address bus transitions for low power memory mapping," in Proc. Int. Symp. Design Automation Test Eur., pp.63-67, 1996.
  9. L. Benini, G. De Micheli, E. Macii, et al., "Asymptotic zero-transition activity encoding for address buses in low-power microprocessor-based systems," in Proc. 7th Great Lakes Symp. VLSI, pp.77-82, 1997.
  10. S. Ramprasad, N. Shanbhag, and I. Hajj, "A coding framework for low power address and data busses," in IEEE Trans. VLSI Syst., Vol.7, pp.212-221, June, 1999. https://doi.org/10.1109/92.766748
  11. Y. Aghaghiri, F. Fallah, and M. Pedram, "Irredundant address bus encoding for low power," in Proc. Int. Symp. Low-Power Electron. Design, 2001, pp.182-187.
  12. L. Macchiarulo, E. Macii, and M. Poncino, "Lowenergy for deep-submicron address buses," in Proc. Int. Symp. Low-Power Electron. Design, pp.176- 181, 2001.
  13. R. R. Rao, H. S. Deogun, D. Blaauw, et al., "Bus Encoding for Total Power Reduction Using a Leakage-Aware Buffer Configuration," IEEE Trans. VLSI Syst., Vol.13, No.12, pp.1376-1383, Dec., 2005. https://doi.org/10.1109/TVLSI.2005.862718
  14. J. Lee, H.-J. Lee, and C. Lee, "A Phase-Based Approach for On-Chip Bus Architecture Optimization," The Computer Journal, Vol.52, No.6, pp.626-645, Aug., 2009. https://doi.org/10.1093/comjnl/bxn059
  15. S. Hong, D. Chung, and Y. Choe, "Selective merging-based reference frame memory compression," in IEEE Pacific Rim Conf. on Communications, Comuters, and Signal Processing, pp.896-900, 2011.
  16. A. Gupte, B. Amrutur, M. Mehendale, A. V. Rao, M. Budagavi, "Memory Bandwidth and Power Reduction Using Lossy Reference Frame Compression in Video Encoding," IEEE Trans. Circuits Syst. Video Techn., Vol.21, pp.225-230, Feb., 2011. https://doi.org/10.1109/TCSVT.2011.2105599
  17. An Introduction to the Intel QuickPath Interconnect, Intel Corporation, Jan. 30, 2009, Retrieved June 14, 2011. [Online] Available: http://www.intel.com/technology/quick path/introduction.pdf.
  18. Collection of test sequences and clips for evaluating compression technology, xiph.org. [Online] Available: http://media.xiph.org/video/derf/
  19. J. Lee, "On-Chip Bus Serialization Method for Low-Power Communications," ETRI Journal, Vol.32, No.4, pp.540-547, Aug., 2010. https://doi.org/10.4218/etrij.10.0109.0447
  20. B.-G. Ahn, J. Kim, W. Li, and J.-W. Chong, "Effective Estimation Method of Routing Congestion at Floorplan Stage for 3D ICs," Journal of Semiconductor Technology and Science, Vol.11, No.4, pp.344-350, Dec., 2011. https://doi.org/10.5573/JSTS.2011.11.4.344