Journal of information and communication convergence engineering

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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Performance Improvement and Power Consumption Reduction of an Embedded RISC Core

  • Jung, Hong-Kyun (Department of Information and Communication Engineering, Hanbat National University) ;
  • Jin, Xianzhe (Department of Information and Communication Engineering, Hanbat National University) ;
  • Ryoo, Kwang-Ki (Department of Information and Communication Engineering, Hanbat National University)
  • Received : 2011.09.01
  • Accepted : 2011.10.20
  • Published : 2012.03.31
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Abstract

This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of an embedded RISC core and a clock-gating algorithm with observability don’t care (ODC) operation to reduce the power consumption of the core. The branch prediction algorithm has a structure using a branch target buffer (BTB) and 4-way set associative cache that has a lower miss rate than a direct-mapped cache. Pseudo-least recently used (LRU) policy is used for reducing the number of LRU bits. The clock-gating algorithm reduces dynamic power consumption. As a result of estimation of the performance and the dynamic power, the performance of the OpenRISC core applied to the proposed architecture is improved about 29% and the dynamic power of the core with the Chartered 0.18 ${\mu}m$ technology library is reduced by 16%.

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References

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