JSTS:Journal of Semiconductor Technology and Science

  • 제12권1호
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  • Pages.99-106
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  • 2012
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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The Impact of Gate Leakage Current on PLL in 65 nm Technology: Analysis and Optimization

  • Li, Jing (School of Microelectronics and Solid-State Electronics, University of Electronic Science and Technology of China) ;
  • Ning, Ning (School of Microelectronics and Solid-State Electronics, University of Electronic Science and Technology of China) ;
  • Du, Ling (School of Microelectronics and Solid-State Electronics, University of Electronic Science and Technology of China) ;
  • Yu, Qi (School of Microelectronics and Solid-State Electronics, University of Electronic Science and Technology of China) ;
  • Liu, Yang (School of Microelectronics and Solid-State Electronics, University of Electronic Science and Technology of China)
  • 투고 : 2011.08.29
  • 발행 : 2012.03.31
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초록

For CMOS technology of 65 nm and beyond, the gate leakage current can not be negligible anymore. In this paper, the impact of the gate leakage current in ring voltage-controlled oscillator (VCO) on phase-locked loop (PLL) is analyzed and modeled. A voltage -to-voltage (V-to-V) circuit is proposed to reduce the voltage ripple on $V_{ctrl}$ induced by the gate leakage current. The side effects induced by the V-to-V circuit are described and optimized either. The PLL design is based on a standard 65 nm CMOS technology with a 1.8 V power supply. Simulation results show that 97 % ripple voltage is smoothed at 216 MHz output frequency. The RMS and peak-to-peak jitter are 3 ps and 14.8 ps, respectively.

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참고문헌

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