JSTS:Journal of Semiconductor Technology and Science

  • 제12권1호
  • /
  • Pages.46-52
  • /
  • 2012
  • /
  • 1598-1657(pISSN)
  • /
  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지
DOI QR코드

DOI QR Code

Avalanche Hot Source Method for Separated Extraction of Parasitic Source and Drain Resistances in Single Metal-Oxide-Semiconductor Field Effect Transistors

  • 투고 : 2011.08.02
  • 발행 : 2012.03.31
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

Separate extraction of source ($R_S$) and drain ($R_D$) resistances caused by process, layout variations and long term degradation is very important in modeling and characterization of MOSFETs. In this work, we propose "Avalanche Hot-Source Method (AHSM)" for simple separated extraction of $R_S$ and $R_D$ in a single device. In AHSM, the high field region near the drain works as a new source for abundant carriers governing the current-voltage relationship in the MOSFET at high drain bias. We applied AHSM to n-channel MOSFETs as single-finger type with different channel width/length (W/L) combinations and verified its usefulness in the extraction of $R_S$ and $R_D$. We also confirmed that there is a negligible drift in the threshold voltage ($V_T$) and the subthreshold slope (SSW) even after application of the method to devices under practical conditions.

키워드

참고문헌

  1. S. C. Williams, et al, "Scaling Trends for Device Performance and Reliability in Channel Engineered n-MOSFET's," IEEE Trans. Electron Devices, Vol.45, No.1, pp.254-260, Jan., 1998. https://doi.org/10.1109/16.658839
  2. H. Iwai, H. S. Momose and Y. Katsumata, "Si-MOSFET scaling down to deep-sub-0.1-micron range and future of silicon LSI," VLSI Technology (Systems and Applications International Symposium), pp.262-267, 1995.
  3. N. Arora, MOSFET Models for VLSI Circuit Simulation, World scientific, 1993, pp.102-108.
  4. S. Cserveny, "Relationship between measured and intrinsic transconductances of MOSFET's," IEEE Trans. Electron Devices, Vol.37, No.11, pp.2413-2414, Nov., 1990. https://doi.org/10.1109/16.62303
  5. J. F. Chen, J. Tao, P. Fang, and C. Hu, "0.35 ${\mu}m$ asymmetric and symmetric LDD device comparison using a reliability/speed/power methodology," IEEE Electron Dev. Lett., Vol.19, No.7, pp.216-218. Jul., 1998. https://doi.org/10.1109/55.701421
  6. J. F. Chen, J. Tao, P. Fang, and C. Hu, "Performance and reliability comparison between asymmetric and symmetric LDD devices and logic gates," IEEE Solid-State Circuits, Vol.34, No.3, pp.367-371, Mar., 1999. https://doi.org/10.1109/4.748188
  7. C. L. Lou, W. K. Chim, D. D. S. Chan, and Y. Pan, "A novel single device DC method for extraction of the effective mobility and source-drain resistance of fresh and hot-carrier degraded drain-engineered MOSFET's," IEEE Trans. Electron Devices, Vol.45, No.6, pp.1317-1323, Jun., 1998. https://doi.org/10.1109/16.678559
  8. H. T. Kim, I. C. Nam, K. S. Kim, K. H. Kim, J. B. Choi, J. U. Lee, S. W. Kim, G. C. Kang, D. J. Kim, K. S. Min, D. W. Kang, and D. M. Kim, "Extraction of the Source and Drain Resistances in MOSFETs using Parasitic Bipolar Junction Transistor," Electronics Lett., Vol.41, No.13, pp.772-774, Jun., 2005. https://doi.org/10.1049/el:20051108
  9. D. M. Kim, H. C. Kim, and H. T. Kim, "Modeling and Extraction of Gate Bias-Dependent Parasitic Source and Drain Resistances in MOSFET's," Solid-State Electronics, Vol.47, No.10, pp.1707-1712, Oct., 2003. https://doi.org/10.1016/S0038-1101(03)00134-5
  10. E. Torres-Rios, R. Torres-Torres, G. Valdovinos-Fierro, and E. A.Gutierrez-D, "A method to determine the gate bias-dependent and gate biasindependent components of MOSFET series resistance from S-parameters," IEEE Trans. Electron Devices, Vol.53, No.3, pp.571-573, Mar., 2006. https://doi.org/10.1109/TED.2006.870328
  11. J. C. Guo, S. S. Chung, and C. C. H. Hsu, "A new approach to determine the effective channel length and drain-and source series resistance of miniaturized MOSFET's," IEEE Trans. Electron Devices, Vol.41, No.10, pp.1811-1818, Oct., 1994. https://doi.org/10.1109/16.324592
  12. A. Ortiz-Conde, J. J. Liou, W. Wong, and F. J. Garcia Sanchez, "Simple method for extracting the difference between the drain and source series resistances in MOSFETs," Electron Lett, Vol.30, No.12, pp.1013-1015, Jun., 1994. https://doi.org/10.1049/el:19940681
  13. A. Raychaudhuri, J. Kolk, M. J. Deen, and M. I. H. King, "A simple method to extract the asymmetry in parasitic source and drain resistances from measurements on a MOS transistor," IEEE Trans. Electron Devices, Vol.42, No.7, pp.1388-1390, Jul., 1995. https://doi.org/10.1109/16.391229
  14. S. H. Jen, C. C. Enz, D. R. Pehlke, M. Schroter, and B. J. Sheu, "Accurate modeling and parameter extraction for MOS transistors valid up to 10 GHz," IEEE Trans. Electron Devices, Vol.46, No.11, pp.2217-2227, Nov., 1999. https://doi.org/10.1109/16.796299
  15. S. Lee, H. K. Yu, C. S. Kim, J. G. Koo, and K. S. Nam, "A novel approach to extract small-signal model parameters of silicon MOSFET's," IEEE Microwave Guided Wave Lett. Vol.7, No.3, pp.75-77, Mar., 1997.
  16. A. T. Hatzopoulos, D. H. Tassis, and C. A. Dimitriadis, and G. Kamarinos, A. T. Hatzopoulos, D. H. Tassis, and C. A. Dimitriadis, and G. Kamarinos, "Analytical on-state current model of polycrystalline silicon thin-film transistors including the kink effect," Appl. Phys. Lett., Vol.87, No.6, p.063501, Aug., 2005. https://doi.org/10.1063/1.2007859
  17. E.-H. Toh, G. H. Wang, L. Chan, G. Samudra, and Y.-C. Yeo, "Reduction of impact-ionization threshold energies for performance enhancement of complementary impact-ionization metal-oxidesemiconductor transistors," Appl. Phys. Lett., Vol.91, No.15, p. 153501, Oct., 2007. https://doi.org/10.1063/1.2798064
  18. R. S. Muller, T. I. Kamins, and M. Chan, Device Electronics for Integrate Circuits, John Wiley & Sons, 2003, pp.490-507.
  19. Y. Taur, T. Ning, Fundamentals of MODERN VLSI DEVICES, Cambridge university press, 1998, pp.158-161.
  20. H. Bae, S. C. Baek, S. Lee, J. Jang, J. S. Shin, D. Yun, H. Kim, D. H. Kim, and D. M. Kim, "Separate Extraction of Source, Drain, and Substrate Resistances in MOSFETs With Parasitic Junction Current Method," IEEE Electron Device Lett., Vol.31, No.11, pp.1190-1192, Nov., 2010.

피인용 문헌

  1. Hybrid Open Drain Method and Fully Current-Based Characterization of Asymmetric Resistance Components in a Single MOSFET vol.63, pp.11, 2016, https://doi.org/10.1109/TED.2016.2607721