Journal of Computing Science and Engineering

Korean Institute of Information Scientists and Engineers (한국정보과학회)
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Static Timing Analysis of Shared Caches for Multicore Processors

  • Zhang, Wei (Department of Electrical and Computer Engineering, Virginia Commonwealth University) ;
  • Yan, Jun (MathWorks Inc.)
  • Received : 2012.04.19
  • Accepted : 2012.11.22
  • Published : 2012.12.30
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Abstract

The state-of-the-art techniques in multicore timing analysis are limited to analyze multicores with shared instruction caches only. This paper proposes a uniform framework to analyze the worst-case performance for both shared instruction caches and data caches in a multicore platform. Our approach is based on a new concept called address flow graph, which can be used to model both instruction and data accesses for timing analysis. Our experiments, as a proof-of-concept study, indicate that the proposed approach can accurately compute the worst-case performance for real-time threads running on a dual-core processor with a shared L2 cache (either to store instructions or data).

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