DOI QR코드

DOI QR Code

Low-Power Design of Hardware One-Time Password Generators for Card-Type OTPs

  • Lee, Sung-Jae (Korea Internet & Security Agency) ;
  • Lee, Jae-Seong (School of Electrical and Computer Engineering, Hanyang University) ;
  • Lee, Mun-Kyu (School of Computer and Information Engineering, Inha University) ;
  • Lee, Sang-Jin (School of Information Management and Security, Korea University) ;
  • Choi, Doo-Ho (Software Research Laboratory, ETRI) ;
  • Kim, Dong-Kyue (School of Electrical and Computer Engineering, Hanyang University)
  • 투고 : 2010.07.05
  • 심사 : 2011.04.07
  • 발행 : 2011.08.30

초록

Since card-type one-time password (OTP) generators became available, power and area consumption has been one of the main issues of hardware OTPs. Because relatively smaller batteries and smaller chip areas are available for this type of OTP compared to existing token-type OTPs, it is necessary to implement power-efficient and compact dedicated OTP hardware modules. In this paper, we design and implement a low-power small-area hardware OTP generator based on the Advanced Encryption Standard (AES). First, we implement a prototype AES hardware module using a 350 nm process to verify the effectiveness of our optimization techniques for the SubBytes transform and data storage. Next, we apply the optimized AES to a real-world OTP hardware module which is implemented using a 180 nm process. Our experimental results show the power consumption of our OTP module using the new AES implementation is only 49.4% and 15.0% of those of an HOTP and software-based OTP, respectively.

키워드

참고문헌

  1. N. Haller and C. Metz, A One-Time Password System, Internet RFC 1938, May 1996.
  2. ISO standards, "Information Technology-Identification Cards- Financial Transaction Cards," ISO/IEC 7813, 2006.
  3. Emerging Issue Report, Korea Institute of Science and Technology Information (KISTI), "The Directions of Future Technologies and Market Competitions of Thin Film Batteries and Thin Lithium Batteries," 2007.
  4. A. Patil et al., "Issue and Challenges Facing Rechargeable Thin Film Lithium Batteries," Mater. Res. Bull., vol. 43, 2008, pp. 1913-1942. https://doi.org/10.1016/j.materresbull.2007.08.031
  5. National Institute of Standards and Technology, "Advanced Encryption Standard," FIPS PUB 197, 2001.
  6. IETF Network Working Group, "HOTP: An HMAC-Based One- Time Password Algorithm," IETF RFC 4226, 2005.
  7. N. Pramstaller and J. Wolkerstorfer, "A Universal and Efficient AES Co-processor for Field Programmable Logic Arrays," FPL , LNCS, vol. 3203, 2004, pp. 565-574.
  8. J. Zambreno, D. Nguyen, and A. Choudhary, "Exploring Area/Delay Tradeoffs in an AES FPGA Implementation," FPL , LNCS, vol. 3203, 2004, pp. 575-585.
  9. P. Chodowiec and K. Gaj, "Very Compact FPGA Implementation of the AES Algorithm," CHES, LNCS, vol. 2779, 2003, pp. 319- 333.
  10. J. Wolkerstorfer, E. Oswald, and M. Lamberger, "An ASIC Implementation of the AES SBoxes," CT-RSA, LNCS, vol. 2271, 2002, pp. 29-52.
  11. A. Satoh et al., "A Compact Rijndael Hardware Architecture with S-Box Optimization," ASIACRYPT, LNCS, vol. 2248, 2001, pp. 239-254
  12. A. Rudra, "Efficient Rijndael Encryption Implementation with Composite Field Arithmetic," CHES, LNCS, vol. 2162, 2001, pp. 171-184.
  13. S. Chantarawong and S. Choomchuay, "An Architecture for a Compact AES System," Proc. 1st Electrical Eng./Electron., Computer, Telecommun. Inf. Technol. (ECTI) Annual Conf., May, 2004.
  14. A. Hodjat and I. Verbauwhede, "A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA." FCCM, Apr., 2004, pp. 308-309.
  15. T. Good and M. Benaissa, "Pipelined AES on FPGA with Support for Feedback Modes (in a Multi-Channel Environment)," IET Information Security, vol. 1, no. 1, 2007, pp. 1-10. https://doi.org/10.1049/iet-ifs:20060059
  16. M. Feldhofer, S. Dominikus, and J. Wolkerstorfer, "Strong Authentication for RFID Systems Using the AES Algorithm," CHES, LNCS, vol. 3156, 2004, pp. 357-370.
  17. ANS X9.52-1998, "Triple Data Encryption Algorithm Modes of Operation," 1999.
  18. Korea Information Security Agency (KISA), "SEED Algorithm Specification," 1999.
  19. Y. Kim and Y. Jeong, "Low Power Implementation of Integrated Cryptographic Engine for Smart Cards," J. Institute Electron. Eng. Korea, vol. 45, no. 372, June 2008, pp. 80-88.
  20. J. Hwang, "Efficient Hardware Architecture of SEED S-Box for Smart Cards," J. Semiconductor Technol. Sci., vol. 4, no. 4, Dec. 2003, pp. 307-311.
  21. M. O'Neill, "Low-Cost SHA-1 Hash Function Architecture for RFID Tags," Hand. of Conf. RFID Security, 2008.
  22. M. Feldhofer, J. Wolkerstorfer, and V. Rijmen, "AES Implementation on a Grain of Sand," IET Proc. Info. Security, vol. 152, no. 1, 2005, pp. 13-20. https://doi.org/10.1049/ip-ifs:20055006
  23. S. Mangard, M. Aigner, and S. Dominikus, "A Highly Regular and Scalable AES Hardware Architecture," IEEE Trans. Comput., vol. 52, no. 4, 2003, pp. 483-491. https://doi.org/10.1109/TC.2003.1190589
  24. D. Kim et al., "Design and Performance Analysis of Electronic Seal Protection Systems Based on AES," ETRI J., vol. 29, no. 6, Dec. 2007, pp. 755-768. https://doi.org/10.4218/etrij.07.0107.0068
  25. W. Athas et al., "Low-Power Digital Systems Based on Adiabatic- Switching Principles," IEEE Trans. VLSI Syst., vol. 2, no. 4, Dec. 1994, pp. 398-407. https://doi.org/10.1109/92.335009

피인용 문헌

  1. Multicolour Fluorescent Memory Based on the Interaction of Hydroxy Terphenyls with Fluoride Anions vol.20, pp.49, 2014, https://doi.org/10.1002/chem.201404089