NAND Flash 메모리를 위한 오류정정부호

  • Published : 2011.08.30

Abstract

본 고에서는 최근 다양한 분야에서 활용되고 있는 NAND flash 메모리 소자를 위한 오류정정 방식에 대한 동향을 소개하고자 한다. 먼저, NAND flash 메모리의 오류가 발생하는 원인을 소개하고 현재 사용되고 있는 오류정정 부호들의 소개 및 가까운 미래의 NAND flash 메모리에서 예상되는 오류 발생원인 및 이에 대처하기 위해 연구가진행 중인 오류정정 부호설계기술들에 대하여 소개하고자 한다.

Keywords

References

  1. K. Kim, "Technology for sub-50 nm DRAM and NAND flash manufacturing," in IEDM Tech. Dig., 2005, pp. 333-336.
  2. K. Kim and J. Choi, "Future outlook of NAND flash technology for 40 nm node and beyond," in IEEE NVSMW Tech. Dig., 2006, pp. 9-11.
  3. T. Kim, S. Lee, J. Park, H. Cho, B. You, K. Baek, J. Lee, C. Yang, M. Yun, M. Kim, J. Kim, E. Jang, H. Chung, S. Lim, B. Han and Y. Koh, "A 32Gb MLC NAND flash memory with Vth margin-expanding schemes in 26nm CMOS," in Proc. of IEEE ISSCC, 2011, pp.202-204, 20-24 Feb. 2011.
  4. K. Park, O. Kwon, S. Yoon, M. Choi. I. Kim, B. Kim, M. Kim, Y. Choi, S. Shin, Y. Song, J. Park, J. Lee, C. Eun, H. Lee, H. Kim, J. Lee, J. Kim, T. Kweon, H. Yoon, T. Kim, D. Shim, J. Sel, J. Shin, P. Kwak, J. Han, K. Kim, S. Lee, Y. Lim and T. Jung, "A 7MB/s 64Gb 3-bit/cell DDR NAND flash memory in 20nm-node technology," in Proc. of ISSCC, 2011, pp.212-213, 20-24 Feb. 2011.
  5. G. Marotta et al., "A 3 bit/cell 32 Gb NAND flash memory at 34 nm with 6 MB/s program throughput and with dynamic 2 b/cell blocks configuration mode for a program throughput increase up to 13 MB/s," in Proc. of IEEE ISSCC, 2010,pp. 444-445.
  6. Y. Li et al, "A 16 Gb 3-bit per cell (X3) NAND flash memory on 56 nm technology with 8 MB/s write rate," IEEE J. of Sol. St. Circuits, vol. 44, pp. 195-207, Jan. 2009. https://doi.org/10.1109/JSSC.2008.2007154
  7. C. Trinh et al., "A 5.6 MB/s 64 Gb 4 b/Cell NAND flash memory in 43 nm CMOS," in Proc. of IEEE ISSCC, Feb. 2009,pp. 246-247.
  8. N. Shibata et al., "A 70 nm 16 Gb 16-level-cell NAND flash memory," IEEE J. Sol. St. Circuits, vol. 43, pp. 929-937, Apr. 2008. https://doi.org/10.1109/JSSC.2008.917559
  9. S. Li and T. Zhang, "Improving multi-level NAND flash memory storage reliability using concatenated BCHTCM coding," IEEE Trans. Circuits and Systems-I: Regular Papers, vol. PP, pp. 1-1, 2009.
  10. R. Bez, E. Camerlinghi, A. Modelli, and A. Visconti, "Introduction to flash memory," in Proc. IEEE, 2003, vol. 91, no. 4, pp. 489-502.
  11. Alan R. Olson, Denis J. Langlois "Solid State Drives Data Reliability and Lifetime," Imation White Paper, April 2008.
  12. N. Mielke, T. Marquart, N. Wu, J. Kessenich, H. Belgal, E. Schares, F. Trivedi, E. Goodness, and L. R. Nevill, "Bit error rate in NAND flash memories," in Proc. IEEE IRPS, 2008, pp. 9-19.
  13. H. Kurata, K. Otsuga, A. Kotabe, S. Kajiyama, T. Osabe, Y. Sasago, S. $Narumi^{\ast}$, K. Tokami, S. Kamohara, O. Tsuchiya, "The Impact of Random Telegraph Signals on the Scaling of Multilevel Flash Memories," IEEE Symp. VLSI Circuits, 2006, pp 112-113.
  14. C. Compagnoni, A. Spinelli, R. Gusmeroli, A. Lacaita, S. Beltrami, A. Ghetti and A. Visconti, "First evidence for injection statistics accuracy limitations in NAND Flash constant-current Fowler-Nordheim programming," IEDM Tech Dig. 2007, pp 165-168.
  15. Lee, J.-D., Hur, S.-H., and Choi, J.-D., "Effects of floating-gate interference on NAND flash memory cell operation," IEEE Trans. Electron Devices, 2002, 23, pp. 264?266.
  16. K. Naruke, S. Taguchi and M. Wada, "Stress Induced Leakage Current Limiting To Scale Down EEPROM Tunnel Oxide Thickness," in Proc. IEDM, pp. 424-427, (1988).
  17. A. Brand, K. Wu, S. Pan and D. Chin, "Novel Read Disturb Failure Mechanism Induced By FLASH Cycling," in Proc. 2003 IRPS, pp 127-132, (1993).
  18. R. Degraeve, F. Schuler, B. Kaczer, M. Lorenzini, D. Wellekens, P, Hendrickx, M. van Duuren, G. Dormans, J. Van Houdt, L. Haspeslagh, G. Groeseneken, G. Tempel, "Analytical percolation model for predicting anomalous charge loss in flash memories," IEEE Trans. Elect. Dev., 51(9), Sept. 2004, pp 1392-1400. https://doi.org/10.1109/TED.2004.833583
  19. H. Belgal, N. Righos, I. Kalastirsky, J. Peterson, R. Shiner, and N. Mielke, "A new reliability model for post-cycling charge retention of flash memories," Proc. 2002 IRPS, pp 7-20.
  20. M. Kato, N. Miyamoto, H. Kume, A. Satoh, T. Adachi, M. Ushiyama and K. Kimura, "Read-disturb degradation mechanism due to electron trapping in the tunnel oxide for low-voltage flash memories," 1994 IEDM Tech. Dig., pp 45-48 (1994).
  21. R. Yamada, Y. Mori, Y. Okuyama, J. Yugami, T. Nishimoto and H. Kume, "Analysis of detrap current due to oxide traps to improve flash memory retention," Proc. 2000 IRPS, pp 200-204 (2000).
  22. R. Yamada, T. Sekiguchi, Y. Okuyama, J. Yugami and H. Kume, "A novel analysis method of threshold voltage shift due to detrap in a multi-level flash memory," Tech. Dig. 2001 VLSI Tech. Symp., pp 115-116.
  23. J. Lee, J. Choi, D. Park, and K. Kim, "Degradation of Tunnel Oxide by FN Current Stress and Its Effects on Data Retention Characteristics of 90-nm NAND Flash Memory," 2003 IRPS, pp. 497, 2003.
  24. N. Mielke, H. Belgal, I. Kalastirsky, P. Kalavade, A. Kurtz, Q. Meng, N. Righos, and J. Wu, "Flash EEPROM Threshold Instabilities due to Charge Trapping During Program/Erase Cycling," IEEE trans. Dev. and Mat. Reliability, vol. 2, No. 3, pp 335-244, 2004.
  25. N. Mielke, H. Belgal, A. Fazio, Q. Meng, and N. Righos, "Recovery Effects in the Distributed Cycling of Flash Memories," Proc. 2006, pp 29-35.
  26. K. Takeuchi, s, Satoh, T. Tanaka, K. Imamiya, K. Sakui, "A negative Vth cell architecture for highly scalable, excellently noise-immune, and highly reliable NAND flash memories," IEEE J. Sol. St. Circuits, 34(5), pp 675-684, May 1999. https://doi.org/10.1109/4.760379
  27. K. Park, M. Kang, D. Kim, S. Hwang, B. Choi, Y. Lee, C. Kim, and K. Kim, "A zeroing cell-to-cell interference page architecture with temporary LSB storing and parallel MSB program scheme for MLC NAND flash memories," IEEE J. Sol. St. Circuits, vol. 43, no. 4, pp. 919-928, Apr. 2008.
  28. G. Dong, S. Li, and T. Zhang, "Using data post-compensation and pre-distortion to tolerate cell-to-cell interference in MLC NAND flash memory," IEEE Trans. Circuits and Systems-I : Regular Papers, vol. 57, no. 10, pp. 2718-2728, 2010. https://doi.org/10.1109/TCSI.2010.2046966
  29. E. Yaakobi, J. Ma, L. Grupp, P. H. Siegel, S. Swanson and J. K. Wolf, "Error Characterization and Coding Schemes for Flash Memories," Workshop on the Application of Communication Theory to Emerging Memory Technologies, 2010.
  30. H. Choi, W Liu, and W Sung, 'VLSI Implementation of BCH Error Correction for Multilevel Cell NAND Flash Memory," IEEE Trans. VLSI Syst., vol. 18, pp. 843-847, July. 2010 https://doi.org/10.1109/TVLSI.2009.2015666
  31. J. Gray and C. van Ingen, "Empirical Measurements of Disk Failure Rates and Error Rates," Microsoft Research Technical Report MSR-TR-2005-166, Dec. 2005
  32. R. G. Gallager, "Low-density parity-check codes," IEEE Trans. Inf. Theory, vol. IT-8, pp. 21-28, Jan. 1962.
  33. C. Berrou, A. Glavieux, and P. Thitimajshima, "Near Shannon limit error-correcting coding and decoding: Turbo-codes," in Proc. of ICC' 93, Geneve, Switzerland, May 1993, pp. 1064-1070.
  34. S. Lin and D. J. Costello, Error Control Coding: Fundamentals and Applications, 2nd ed, Englewood Cliffs, NJ: Prentice-Hall, 2004.
  35. G. Dong, N. Xie, and T. Zhang, "On the use of soft-decision error-correction codes in NAND flash memory," IEEE Trans. Circuits and Systems-I : Regular Papers, vol. 58, no. 2, pp. 429-439, 2011. https://doi.org/10.1109/TCSI.2010.2071990
  36. G. Ungerboeck, "Trellis-coded modulation with redundant signal sets part I, II," IEEE Commun. Mag., vol. 25, no. 2, pp. 5-21, Feb. 1987.
  37. A. Jiang, R Mateescu, M. Schwartz, and J. Bruck, "Rank modulation for flash memories," in Proceedings IEEE ISIT 2008, Toronto, Canada, July 2008.
  38. G. D. Cohen, P. Godlewski, and F. Merkx, "Linear binary code for write-once memories," IEEE Trans. Inf. Theory, vol. IT-32,no. 5,pp. 697-700, Sep, 1986.
  39. A. Fiat and A. Shamir, "Generalized write-once memories," IEEE Trans. Inf. Theory, vol. IT-30, no. 3, pp. 470-480, May 1984.