Transactions on Electrical and Electronic Materials

The Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회)
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Study of Via-Typed Air-Gap for Logic Devices Applications below 45 nm Node

  • Kim, Sang-Yong (Department of Semiconductor System, Korea Polytechnic College IV) ;
  • Kim, Il-Soo (Department of Semiconductor System, Korea Polytechnic College IV) ;
  • Jeong, Woo-Yang (Department of Semiconductor System, Korea Polytechnic College IV)
  • Received : 2011.03.08
  • Accepted : 2011.06.02
  • Published : 2011.08.25
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Abstract

Back-end-of-line using ultra low-k (ULK; k < 2.5) has been required to reduce resistive capacitance beyond 45 nmtechnologies, because micro-processing units need higher speed and density. There are two strategies to manufacture ULK inter-layer dielectric (ILD) materials using an air-gap (k = 1). The former ULK and calcinations of ILD degrade the mechanical strength and induce a high cost due to the complication of following process, such as chemical mechanical polishing and deposition of the barrier metal. In contrast, the air-gap based low-k ILD with a relatively higher density has been researched on the trench-type with activity, but it has limited application to high density devices due to its high air-gap into the next metal layer. The height of air-gap into the next metal layer was reduced by changing to the via-typed air-gap, up to about 50% compared to that of the trench-typed air-gap. The controllable ULK was easily fabricated using the via-typed air-gap. It is thought that the via-type air-gap made the better design margin like via-patterning in the area with the dense and narrow lines.

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References

  1. J. Faguet, E. Lee, J. Liu, J. Brcka, and O. Akiyama, IEEE International Interconnect Technology Conference (Sapporo, Japan 2009 Jun. 1-3) p. 35. [DOI: 10.1109/IITC.2009.5090333].
  2. K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau, C. H. Choi, G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He, J. Hicks, R. Huessner, D. Ingerly, P. Jain, R. James, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz, B. McIntyre, P. Moon, J. Neirynck, S. Pae, C. Parker, D. Parsons, C. Prasad, L. Pipes, M. Prince, P. Rarade, T. Reynolds, J. Sandford, L. Shifren, J. Sebastian, J. Seiple, D. Simon, S. Sivakumar, P. Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams, and K. Zawadzki, IEEE International Electron Devices Meeting (Washington, DC 2007 Dec. 10-12) p. 247. [DOI: 10.1109/IEDM.2007.4418914].
  3. M. Gallitre, A. Farcy, B. Blampey, C. Bermond, B. Flechet, and P. Ancey, Microelectron. Eng. 87, 321 (2010) [DOI: 10.1016/j.mee.2009.09.003].
  4. H. Park, M. Kraatz, J. Im, B. Kastenmeier, and P. S. Ho, Advanced Nanoscale ULSI Interconnects: Fundamentals and Applications ed. Y. Shacham-Diamand, M. Datta, T. Osaka, and T. Ohba (Springer New York, 2009) p. 153. [DOI: 10.1007/978-0-387-95868-2_11].
  5. K. Chan and K. K. Gleason, J. Electrochem. Soc. 153, C223 (2006) [DOI: 10.1149/1.2168297].
  6. R. Daamen, P. H. L. Bancken, V. H. Nguyen, A. Humbert, G. J. A. M. Verheijden, and R. J. O. M. Hoofman, Microelectron. Eng. 84, 2177 (2007) [DOI: 10.1016/j.mee.2007.04.119].
  7. A. Piontek, T. Vanhoucke, S. Van Huylenbroeck, L. J. Choi, G. A. M. Hurkx, E. Hijzen, and S. Decoutere, Semicond. Sci. Technol. 22, S9 (2007) [DOI: 10.1088/0268-1242/22/1/s03].
  8. T. Ueda, T. Harada, A. Ueki, S. Kido, K. Tomita, Y. Kanda, T. Sasaki, H. Tsuji, T. Furuhashi, T. Kabe, J. Shibata, A. Iwasaki, J. Izumitani, Y. Kawano, and S. Matsumoto, AIP Conf. Proc. 1,143, 172 (2009) [DOI: 10.1063/1.3169257].
  9. C. J. Wilson, C. Zhao, L. Zhao, T. H. Metzger, Z. Tkei, K. Croes, M. Pantouvaki, G. P. Beyer, A. B. Horsfall, and A. G. O'Neill, Appl. Phys. Lett. 94, 181914 (2009) [DOI: 10.1063/1.3133345].
  10. J. Yuan, C. Ye, Z. Xing, Y. Xu, and Z. Ning, Microelectron. Eng. 86, 2119 (2009) [DOI: 10.1016/j.mee.2009.02.023].