Journal of Information Processing Systems

  • 제7권1호
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  • Pages.93-102
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  • 2011
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  • 1976-913X(pISSN)
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  • 2092-805X(eISSN)
한국정보처리학회 (Korea Information Processing Society)
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Dynamic Voltage and Frequency Scaling for Power-Constrained Design using Process Voltage and Temperature Sensor Circuits

  • Nan, Haiqing (Dept. of Electronics and Computer Engineering, Illinois Institute of Technology) ;
  • Kim, Kyung-Ki (School of Electronic Engineering, Daegu University) ;
  • Wang, Wei (Dept. of Electronics and Computer Engineering, Illinois Institute of Technology) ;
  • Choi, Ken (Dept. of Electronics and Computer Engineering, Illinois Institute of Technology)
  • 투고 : 2010.08.04
  • 심사 : 2010.08.31
  • 발행 : 2011.03.31
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초록

In deeply scaled CMOS technologies, two major non-ideal factors are threatening the survival of the CMOS; i) PVT (process, voltage, and temperature) variations and ii) leakage power consumption. In this paper, we propose a novel post-silicon tuning methodology to scale optimum voltage and frequency "dynamically". The proposed design technique will use our PVT sensor circuits to monitor the variations and based on the monitored variation data, voltage and frequency will be compensated "automatically". During the compensation process, supply voltage is dynamically adjusted to guarantee the minimum total power consumption without violating the frequency requirement. The simulation results show that the proposed technique can reduce the total power by 85% and the static power by 53% on average for the selected ISCAS'85 benchmark circuits with 45 nm CMOS technology compared to the results of the traditional PVT compensation method.

키워드

참고문헌

  1. N.S. Kim, J. Seomun, A. Sinkar, J. Lee, T.H. Han, K. choi, and Y. Shin, “Frequency and yield optimization using power gates in power-constrained designs,” in Proc. ISLPED, 2009, pp.121-126.
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  8. K. K. Kim and Y. B. Kim, “A Novel Adaptive Design Methodology for Minimum Leakage Power Considering PVT Variations on Nanoscale VLSI Systems,” IEEE Tran. on VLSI systems, Vol.17, No.4, 2009, pp.517-528. https://doi.org/10.1109/TVLSI.2008.2007958
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피인용 문헌

  1. Revisiting reorder buffer architecture for next generation high performance computing vol.65, pp.2, 2013, https://doi.org/10.1007/s11227-011-0734-x
  2. Timing Yield Slack for Timing Yield-Constrained Optimization and Its Application to Statistical Leakage Minimization vol.21, pp.10, 2013, https://doi.org/10.1109/TVLSI.2012.2220792