References
- P. Saxena, R. S. Shelar and S. S. Sapatnekar, Routing Congestion in VLSI Circuit: Estimation and Optimization, Springer, 2007.
- C. Sham, E. Y. Young and J. Lu, "Congestion Prediction in Early Stages of Physical Design," ACM Trans. on Design Automation of Electronic Systems, Vol.14, No.1, Article 12, Jan., 2009.
- Y. Hsieh and T. Hsieh, "A new effective congestion model in floorplan design," Design, Automation and Test in Europe Conf. and Exhibition, 2004. Proc., Vol.2, pp.1204-1209, Feb., 2004.
- X. Yang, R. Kastner and M. Sarrafzadeh, "Congestion estimation during top-down placement," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol.21, No.1, pp.72-80, Jan., 2002. https://doi.org/10.1109/43.974139
- L. Cheng, W. N. N. Hung, G. Yang and X. Song, "Congestion estimation for 3D routing," VLSI, 2004. Proc. IEEE Computer society Annual Symp. on, pp.239- 240, 19-20, Feb., 2004.
- D. H. Kim and S. K. Lim, "Through-silicon-viaaware delay and power prediction model for buffered interconnects in 3D ICs," in Proc. of the 12th ACM/IEEE int. workshop on System level interconnect prediction (SLIP '10), pp.25-32, 2010.
- Z. Payman, J. A. Davis, W. Loh, and J. D. Meindl, "Prediction of interconnect fan-out distribution using Rent's rule," SLIP'00, 2000.
- J. Rosenfeld and E. G. Friedman, "Design methodology for global resonant H-tree clock distribution networks," in Proc. IEEE Int. Symp. Circuits Syst., pp.2073-2076, 2006.
- X. Zhao and S. K. Lim, "Power and slew-aware clock network design for through-silicon-via (TSV) based 3D ICs," Design Automation Conf. (ASPDAC), 2010 15th Asia and South Pacific, pp.175- 180, 18-21 Jan., 2010.
- K. D. Boese and A. B. Kahng, "Zero-skew clock routing trees with minimum wirelength," Proc. 5th Annu. IEEE Int. ASIC Conf. Exhibit, pp.17-21, Sep., 1992.
- P.Falkenstern, Y. Xie, Y. Chang and Y. Wang, "Three-dimensional integrated circuits (3D IC) Floorplan and Power/Ground Network Co-synthesis," Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific, pp.169-174, Jan., 2010.
- J. A. Davis and J. D. Meindl, Interconnect Technology and Design for Gigascale Integration, Kluwer Academic Publishers, 2003.
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