전기학회논문지 (The Transactions of The Korean Institute of Electrical Engineers)

  • 제60권2호
  • /
  • Pages.320-324
  • /
  • 2011
  • /
  • 1975-8359(pISSN)
  • /
  • 2287-4364(eISSN)
대한전기학회 (The Korean Institute of Electrical Engineers)
권호 표지
DOI QR코드

DOI QR Code

카운터 기반 디지털 보상 기법을 이용한 위상 고정 루프

Phase-Locked Loops using Digital Calibration Technique with counter

  • 정찬희 (고려대 공과대 나노반도체학과) ;
  • ;
  • 이관주 (고려대 공과대 전자전기공학과) ;
  • 김훈기 (고려대 공과대 전자전기공학과) ;
  • 김수원 (고려대 전자전기공학과)
  • 투고 : 2010.12.16
  • 심사 : 2011.01.24
  • 발행 : 2011.02.01
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

A digital technique is adopted to calibrate the current mismatch of the charge pump (CP) in phase-locked loops. A 2 GHz charge pump PLL (CPPLL) is used to justify the proposed calibration technique. The proposed digital calibration technique is implemented simply using a counter. The proposed calibration technique reduces the calibration time by up to a maximum of 50% compared other with techniques. Also by using a dual-mode CP, good current matching characteristics can be achieved to compensate $0.5{\mu}A$ current mismatch in CP. It was designed in a standard $0.13{\mu}m$ CMOS technology. The maximum calibration time is $33.6{\mu}s$ and the average power is 18.38mW with 1.5V power supply and effective area is $0.1804mm^2$.

키워드

참고문헌

  1. B. Razavi., Design of Analog CMOS Integrated Circuits, New York:MCgraw-Hill, 2001.
  2. T. A. D. Riley, N. M. Filiol, Q. Du, and J. Kostamovaara, "Techniques for in-band phase noise reduction in ${\Sigma}{\Delta}$ synthesizers," IEEE Transactions on Circuits and Systems-II, Analog Digital Signal Processing, vol. 50, no. 11, pp. 794-803, Nov. 2003. https://doi.org/10.1109/TCSII.2003.819132
  3. W. Rhee, "Design of high-performance CMOS charge pumps in phase-locked loops," in Proceeding IEEE International Symposium on Circuits and Systems, Jun. 1999, vol. 2, pp. 545-548.
  4. Y.-S. Choi and D.-H. Han, "Gain-boosting charge pump for current matching in phase-locked loop," IEEE Transactions on Circuits Systems. II, Express Briefs, vol. 53, no. 10, pp. 1022-1025, Sep. 2006. https://doi.org/10.1109/TCSII.2006.882122
  5. N. D. Dalt and C. Sandner, "sub-picosecond jitter PLL for clock generation in 0.12$\mum$ digital CMOS," IEEE Journal of Solid-State Circuits, vol. 38, no. 7, pp. 1275-1278, Jul. 2003. https://doi.org/10.1109/JSSC.2003.813287
  6. C.-F. Liang, S.-H. Chen and S.-I. Liu, "digital--calibration technique for charge pumps in Phase-locked systems," IEEE Journal of Solid-State Circuits, vol. 43, no. 2, pp. 390-398, Feb. 2008. https://doi.org/10.1109/JSSC.2007.914283