DOI QR코드

DOI QR Code

캐패시터 부정합 보정 기능을 가진 8비트 스위치-캐패시터 사이클릭 D/A 변환기 설계

A Design of 8-bit Switched-Capacitor Cyclic DAC with Mismatch Compensation of Capacitors

  • 양상혁 (고려대 공대 전기전자공학과) ;
  • 송지섭 (고려대 공대 나노반도체공학과) ;
  • 김석기 (고려대 공대 전기전자전파공학과) ;
  • 이계신 ;
  • 이용민 (선문대 정보디스플레이학과)
  • 투고 : 2010.12.16
  • 심사 : 2011.01.24
  • 발행 : 2011.02.01

초록

A switched-capacitor cyclic DAC scheme with mismatch compensation of capacitors is designed. In cyclic DAC, a little error between two capacitors is accumulated every cycle. As a result, the accumulated error influences the final analog output which is wrong data. Therefore, a mismatch compensation technique was proposed and the error can be effectively reduced, which alleviates the matching requirement. In order to verify the operation of the proposed DAC, an 8-bit switched-capacitor cyclic DAC is designed through HSPICE simulation and implemented through magna 0.18um standard CMOS process.

키워드

참고문헌

  1. M. Bell, "An LCD column driver using a switch capacitor DAC," IEEE J. Solid-State Circuits, vol. 40, No. 12, pp. 2756-2765, 2005. https://doi.org/10.1109/JSSC.2005.858481
  2. C. Lu, and L. Hwang, "A 10 bit LCD column driver with piecewise linear digital-to-analog converter," IEEE J. Solid-State Circuits, vol. 43, No. 2, pp. 371-378, 2008. https://doi.org/10.1109/JSSC.2007.914274
  3. Y.K. Choi, et al, "A compact low-power CDAC architecture for mobile TFT-LCD driver ICs," IEEE ISSCC, San Francisco, CA, USA, pp. 176-177, 2008.
  4. P. Chen, and T. Liu, "Switching schemes for reducing capacitor mismatch sensitivity of quai-passive cyclic DAC," IEEE Trans. Circuits Syst. II, vol. 56, No. 1, pp. 26-30, 2009. https://doi.org/10.1109/TCSII.2008.2010158
  5. K.S. Lee, and Y.M. Lee, "Switched-capacitor cyclic DAC with mismatch charge compensation," Electron. Lett, vol. 46, No. 13, pp. 902-903, 2010. https://doi.org/10.1049/el.2010.1182