참고문헌
- Seokjin Lee, Wong. M.D.F. "Timing-driven routing for FPGAs based on Lagrangian relaxation." Computer- Aided Design of Integrated Circuits and Systems. IEEE Transactions on Volume 22, Issue 4, pp. 506-510, April 2003. https://doi.org/10.1109/TCAD.2003.809645
- Togawa, N., Sato, M., Ohtsuki, T. "A simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs." Design Automation Conference 1997. Proceedings of the ASP-DAC '97. Asia and South Pacific, pp. 569- 578, 2 Jan. 1997.
- Yao-Wen Chang; Wong, D.F., Wong, C.K. "FPGA global routing based on a new congestion metric." Computer Design : VLSI in Computers and Processors, 1995. ICCD '95. Proceedings., 1995 IEEE International Conference on Oct. p. 372-378, 1995.
- Togawa, N., Yanagisawa, M., Ohtsuki, T. "Maple-opt : a performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGAs." CAD of IC and system, IEEE Trans. on Vol. 17, Issue 9, pp. 803-818, 1998. https://doi.org/10.1109/43.720317
- Jariwala, D., Lillis, J. "On interactions between routing and detailed placement" Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on pp. 7-11, Nov. 2004.
- Neaton, J. A., Lavin, J. "L4 : An FPGA-Based acceleration for detailed Maze Routing," FPL 2007. Int. Conf., on Aug. pp. 579-584, 2007.
- Madhukar R. Korupoly, k. k. Lee, D.F.Wong. "Exact : Tree-based FPGA Technology Mapping for Logic Blocks with Independent LUTs" Proc. ADC 37th, pp. 704-708, June, 1999.
- Jariwala, D.; Lillis, J.; "RBI : Simultaneous Placement and Routing Optimization Technique." Computer- Aided Design of Integrated Circuits and System, IEEE Transactions on Volume 26., Issue 1, pp. 127-141, Jan 2007. https://doi.org/10.1109/TCAD.2006.883918