반도체디스플레이기술학회지 (Journal of the Semiconductor & Display Technology)

한국반도체디스플레이기술학회 (The Korean Society Of Semiconductor & Display Technology)
권호 표지

A Study on the Minimization of Layout Area for FPGA

  • Yi, Cheon-Hee (Dept. of Electronic Engineering. Chongju University)
  • 투고 : 2010.05.06
  • 심사 : 2010.06.15
  • 발행 : 2010.06.30
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초록

This paper deals with minimizing layout area of FPGA design. FPGAs are becoming increasingly important in the design of ASICs since they provide both large scale integration and user-programmability. This paper describes a method to obtain tight bound on the worst-case increase in area when drivers are introduced along many long wires in a layout. The area occupied by minimum-area embedding for a circuit can depend on the aspect ratio of the bounding rectangle of the layout. This paper presents a separator-based area-optimal embeddings for FPGA graphs in rectangles of several aspect ratios which solves the longest path problem in the constraint graph.

키워드

참고문헌

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