Cost-Driven Optimization of Defect-Avoidant Logic Mapping Strategies for Nanowire Reconfigurable Crossbar Architecture

Nanowire Reconfigurable Crossbar 구조를 위한 결함 회피형 로직 재할당 방식의 분석과 총 비용에 따른 최적화 방안

  • Received : 2010.02.27
  • Accepted : 2010.08.09
  • Published : 2010.10.15

Abstract

As the end of photolithographic integration era is approaching fast, numerous nanoscale devices and systems based on novel nanoscale materials and assembly techniques are recently emerging. Notably, various reconfigurable architectures with considerable promise have been proposed based on nanowire crossbar structure as the primitive building block. Unfortunately, high-density sys-tems consisting of nanometer-scale elements are likely to have numerous physical imperfections and variations. Therefore, defect-tolerance is considered as one of the most exigent challenges in nanowire crossbar systems. In this work, three different defect-avoidant logic mapping algorithms to circumvent defective crosspoints in nanowire reconfigurable crossbar systems are evaluated in terms of various performance metrics. Then, a novel method to find the most cost-effective repair solution is demonstrated by considering all major repair parameters and quantitatively estimating the performance and cost-effectiveness of each algorithm. Extensive parametric simulation results are reported to compare overall repair costs of the repair algorithms under consideration and to validate the cost-driven repair optimization technique.

Photolithography 통합 시대의 끝이 빠르게 다가옴에 따라, 최근에는 새로운 나노 스케일의 소재와 집적 방식에 기반을 둔 수많은 나노 스케일 장치와 시스템이 나타나고 있다. 특히 nanowire crossbar 구조를 이용한 다양한 reconfigurable architecture 들이 보고되고 있다. 하지만 아쉽게도 나노 스케일의 구성 요소를 이용한 이러한 고집적 시스템은 생산 단계에서 발생하는 각종 물리적 결함과 오차에 취약하며 따라서 결함에 대한 관용성 즉 defecttolerance는 nanowire reconfigurable crossbar 시스템에 있어 해결해야 할 가장 중대한 문제 중 하나라 할 수 있다. 이에 본 논문에서는 nanowire reconfigurable crossbar 시스템 상에서 사용되어질 수 있는 세 가지의 결함 회피형(defectavoidant) 로직 재할당 알고리듬을 설명하고 다양한 방식으로 평가하였다. 이에 더불어 로직 재할당시에 발생하는 비용과 이로 인해 얻어지는 repair performance를 계량적으로 상호 분석하여 최적화된 repair 방식을 찾아내는 새로운 방안을 소개하였다. 이어 다양한 파라메터들을 이용한 시뮬레이션 결과를 제시함으로써 새로 소개된 cost-driven repair 최적화 방식을 검증하였다.

Keywords

Acknowledgement

Supported by : 우석대학교

References

  1. International Technology Roadmap for Semiconductors, "International Technology Roadmap for Semiconductors (ITRS) 2004," http://public.itrs.net, 2004.
  2. G. Bourianoff, "The future of nanocomputing," IEEE Computer, vol.38, no.8, pp.44-53, August 2003.
  3. S. C. Goldstein and M. Budiu, "Nanofabrics: spatial computing using molecular nanoelectronics," in Proc. 28th Int. Symp. Computer Architecture, 2001, pp.178-189, 2001.
  4. S. C. Goldstein and D. Rosewater, "Digital logic using molecular electronics," Int. Solid-State Circuits Conf., p.125, 2002.
  5. M. Mishra and S. Goldstein, "Scalable defect tolerance for molecular electronics," Workshop Non-Silicon Computation (NSC-1), p.78, 2002.
  6. T. Rueckes, K. Kim, E. Joselevich, G. Y. Tseng, C. L. Cheung and C. M. Lieber, "Carbon nanotube based nonvolatile random access memory for molecular computing," Science, vol.289, pp.94-97, 2000. https://doi.org/10.1126/science.289.5476.94
  7. P. J. Kuekes, J. R. Heath, and R. S. Williams, "Molecular wire crossbar memory," U.S. Patent 6 128 214, October 2000.
  8. Y. Chen, G. Jung, D. A. A. Ohlberg, X. Li, D. R. Stewart, J. O. Jeppesen, K. A. Nielsen, J. F. Stoddart and R. S. Williams, "Nanoscale molecular- switch crossbar circuits," Nanotechnology, no.14, pp.462-468, 2003.
  9. M. Ziegler and M. Stan, "Design and analysis of crossbar circuits for molecular nanoelectronics," IEEE Conf. Nanotechnology (IEEE-NANO), pp.323-327, 2002.
  10. P. J. Kuekes, J. R. Heath and R. S. Williams, "Molecular-wire crossbar interconnect (MWCI) for signal routing and communications," U.S. Patent 6 314 019, November 2001.
  11. P. J. Kuekes and R. S. Williams, "Demultimplexer for a molecular wire crossbar network (MWCN DEMUX)," U.S. Patent 6 256 767, July 2001.
  12. M. Ziegler and M. Stan, "A case for CMOS/nano co-design," Int. Conf. Computer Aided Design (ICCAD), pp.348-352, 2002.
  13. M. Stan, "A scaling scenario for nanoelectronic technologies," Georgia Tech Conf. Nanoscience and Nanotechnology, p.103, 2001.
  14. N. Melosh, A. Boukai, F. Diana, B. Gerardot, A. Badolato, P. Petroff and J. Heath, "Ultrahighdensity nanowire lattices and circuits," Science, vol.300, p.112-115, April 2003. https://doi.org/10.1126/science.1081940
  15. S. R. Nicewarner-Pena, S. Raina, G. P. Goodrich, N. V. Fedoroff and C. D. Keating, "Hybridization and extension of Au nanoparticle-bound oligonucleotides," Journal of American Chem. Soc., vol.124, pp.7314-7323, 2002. https://doi.org/10.1021/ja0177915
  16. Y. Huang, X. Duan, Q. Wei and C. M. Lieber, "Directed assemble of one-dimensional nanostructures into functional networks," Science, vol.291, pp.630-633, January 2001. https://doi.org/10.1126/science.291.5504.630
  17. Y. Huang, X. Duan, Y. Cui, L. Lauhon, K. Kim and C. M. Lieber, "Logic gates and computation from assembled nanowire building blocks," Science, vol.294, pp.1313-1317, 2001. https://doi.org/10.1126/science.1066192
  18. Y. Cui and C. M. Lieber, "Functional nanoscale electronic devices assembled using silicon nanowire building blocks," Science, vol.291, pp.851-853, February 2001. https://doi.org/10.1126/science.291.5505.851
  19. J. Huang, M. B. Tahoori and F. Lombardi, "On the defect tolerance of nano-scale two-dimensional crossbars," IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp.96-104, October 2004.
  20. M. Jacome, C. He, G. de Veciana, and S. Bijansky, "Defect tolerant probabilistic design paradigm for nanotechnolo-gies," IEEE/ACM Design Automation Conference (DAC), pp.1-6, 2004.
  21. M. Tehranipoor, "Defect Tolerance for Molecular Electronics-Based NanoFabrics Using Built-In Self-Test Procedure," IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Submitted for publication.
  22. J. R. Heath, P. J. Kuekes, G. S. Snider, and R. S. Williams, "A defect-tolerant computer architecture: Opportunities for nanotechnology," Science, vol.280, pp.1716-1721, 1998. https://doi.org/10.1126/science.280.5370.1716
  23. D. Whang, S. Jin and C. M. Lieber, "Large-Scale Hierarchical Organization of Nanowires for Functional Nanosystems," Japanese Journal of Applied Physics, vol.43, no.7B, 2004.
  24. A. Bachtold, P. Hadley, T. Nakanishi and C. Dekker, "Logic circuits with carbon nanotube transistors," Science, vol.294, pp.1317-1320, November 2001. https://doi.org/10.1126/science.1065824
  25. V. Derycke, R. Martel, J. Appenzeller and Ph. Avouris, "Carbon nanotube inter- and intramolecular logic gates," Nano Letter, vol.1, no.9, pp.453-456, 2001. https://doi.org/10.1021/nl015606f
  26. C. Soh, C. Quate, C. Morpurgo, C. Marcus, C. Kong and C. Dai, "Integrated nanotube circuits: controlled growth and ohmic contacting of singlewalled carbon nanotubes," Appled Physics Letter, vol.75, no.5, pp.627-629, 1999. https://doi.org/10.1063/1.124462
  27. S. J. Trans, A. R. M. Verschueren and C. Dekker, "Room-temperature transistor based on a single carbon nanotube," Nature, vol.393, pp.49-51, May 1998. https://doi.org/10.1038/29954
  28. H. Finkelstein, P. M. Asbeck and S. Esener, "Architecture and analysis of a self-assembled 3D array of carbon nanotubes and molecular memories," IEEE Conference on Nanotechnology, pp.12-14, August 2003.
  29. C. Dekker, "Carbon nanotubes as molecular quantum wires," Physics Today, pp.22-28, May 1999.
  30. M. Ziegler, G. Rose and M. Stan, "A universal device model for nanoelectronic circuit simulation," IEEE Conf. Nanotechnology (IEEE-NANO), pp.83- 88, 2002.
  31. M. Bhattacharya and P. Mazumder, "Augmentation of SPICE for simulation of circuits containing resonant tunneling diodes," IEEE Trans. Computer-Aided Design, vol.20, pp.39-50, January 2001. https://doi.org/10.1109/43.905673
  32. J. Chen, W. Wang, M. A. Reed, M. Rawlett, D. W. Price and J. M. Tour, "Room-Temperature Negative Differential Resistance in Nanoscale Molecular Junctions," Appl. Phys. Lett., vol.77, p.1224, 2000. https://doi.org/10.1063/1.1289650
  33. J. Chen, M. A. Reed, A. M. Rawlett and J. M. Tour, "Large on-off ratios and negative differential resistance in a molecular electronic device," Science, vol.286, pp.1550-1552, November 1999. https://doi.org/10.1126/science.286.5444.1550
  34. R. H. Mathews, J. P. Sage, T. C. L. G. Sollner, S. D. Calawa, C. L. Chang-Lee Chen, L. J. Mahoney, P. A. Maki and K. M. Molvar, "A new RTD-FET logic family," Proc. IEEE, vol.87, pp.596-605, April 1999. https://doi.org/10.1109/5.752517
  35. Y. S. Yu, Y. I. Jung, J. H. Park, S. W. Hwang and D. Ahn, "Simulation of single-electron/CMOS hybrid circuits using SPICE macromodeling," J. Korean Phys. Soc., vol.20, no.35, pp.991-994, 1999.
  36. P. Franzon and D. Nackashi, "Moletronics: a circuit design perspective," Int. Conf. SPIE Smart Electronics and MEMS, vol.4236, pp.80-88, 2000.
  37. J. C. Ellenbogen and J. C. Love, "Architectures for molecular electronic computers. I. Logic structures and an adder designed from molecular electronic diodes," Proc. IEEE, vol.88, pp.386-426, March 2000. https://doi.org/10.1109/5.838115
  38. C. J. Christian, J. Amsinck, D. P. David, P. Nackashi, N. H. Neil, H. D. Spigna and P. D. Franzon, "Electrically accessible molecular memories," IEEE J. Nanotechnol., submitted for publication.
  39. R. M. Metzger et al, "Unimolecular electrical rectification in hexadecylquinolinium tricyanoquinodimethanide," J. Amer. Chem. Soc., vol.119, pp.10455-10466, 1997. https://doi.org/10.1021/ja971811e
  40. A. DeHon, "Array-Based Architecture for FETBased, Nanoscale Electronics," IEEE Transactions on Nanotechnology, vol.2, no.1, pp.23-32, March 2003. https://doi.org/10.1109/TNANO.2003.808508
  41. A. Dehon, M. J. Wilson, "Nanowire-Based Sublithographic Programmable Logic Arrays," FPGA'04, Monterey, CA, February, 2004.
  42. H. Naeimi and A. DeHon, "A greedy algorithm for tolerating defective crosspoints in nanoPLA design," IEEE International Conference on Field-Programmable Technology, pp.49-56, 2004.
  43. H. C. Liang, W. C. Ho and M. C. Cheng, "Identify unrepairability to speed-up spare allocation for repairing memories," IEEE Transactions on Reliability, vol.54, no.2, pp.358-365, June 2005. https://doi.org/10.1109/TR.2005.847248
  44. J. F. Li, J. C. Yeh, R. F. Huang and C. W. Wu, "A Built-In Self-Repair Design for RAMs With 2-D Redundancy," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.13, no.6, pp.742-745, June 2005. https://doi.org/10.1109/TVLSI.2005.848824
  45. C. T. Huang and C. F. Wu, J. F. Li and C. W. Wu, "Built-in redundancy analysis for memory yield improvement," IEEE Transactions on Reliability, vol.52, no.4, pp.386-399, December 2003. https://doi.org/10.1109/TR.2003.821925
  46. M. Choi and N. Park, "Dynamic yield analysis and enhancement of FPGA reconfigurable memory systems," IEEE Transactions on Instrumentation and Measurement, vol.51, no.6, pp.1300-1311, December 2002. https://doi.org/10.1109/TIM.2002.808046
  47. W. K. Huang, Y.-N. Shen and F. Lombardi, "New approaches for the repairs of memories with redundancy by row/column deletion for yield enhancement," IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, vol.9, no.3, pp.323-328, Mar 1990. https://doi.org/10.1109/43.46807
  48. Y. Yallambalase and M. Choi, "Cost-driven repair optimization of reconfigurable nanowire crossbar systems with clustered defects," Journal of Systems Architecture, vol.54, no.8, pp.729-741, 2008. https://doi.org/10.1016/j.sysarc.2008.01.001
  49. S. C. Smith, R. F. DeMara, J. S. Yuan, D. Ferguson, and D. Lamb, "Optimization of NULL Convention Self-Timed Circuits," Integration, The VLSI Journal, vol.37, no.3, pp.135-165, 2004. https://doi.org/10.1016/j.vlsi.2003.12.004
  50. R. Bonam, S. Chaudhary, Y. Yellambalase and M. Choi, "Clock-Free Nanowire Crossbar Architecture based on Null Convention Logic (NCL)," 7th IEEE International Conference on Nanotechnology (IEEENano), Apr 2007.
  51. S. Zhang, M. Choi, N. Park and F. Lombardi "Cost-Driven Optimization of Fault Coverage in Combined Built-In Self-Test/Automated Test Equipment Testing," IMTC 04, 2004.