JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Timing Analysis Techniques Review for sub-30 nm Circuit Designs

  • Received : 2010.12.01
  • Published : 2010.12.31
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Abstract

With scaled technology, timing analysis of circuits becomes more and more difficult. In this paper, we review recently developed circuit simulation techniques created to deal with the cost issues of transistor-level simulations. Various techniques for fast SPICE simulations and Monte Carlo simulations are introduced. Moreover, process and aging variation issues are mentioned, along with promising methodologies.

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References

  1. Xin Li, Jiayong Le, and Lawrence T. Pileggi, Statistical Performance Modeling and Optimization, Lightining Source Inc., 2007.
  2. ITRS 2009 Design Roadmap, http://www.itrs.net/Links/2009ITRS
  3. Sang Phill Park, K. Roy, and K. Kang,“Reliabiliability Implications of Bias-Temperature Instability in Digital ICs,” IEEE Design and Test of Computers, Vol.26, No.6, pp.8-17, 2009. https://doi.org/10.1109/MDT.2009.154
  4. K. Gulati, J. F. Croix, S. P. Khatri, and R. Shastry, “Fast Circuit Simuation on Graphics Processing Units,” Asia and South Pacific Design Automation Conference (ASP-DAC), pp.403-408, Jan. 2009.
  5. X. Zhou, Y. Wang, and H. Yang, “DCCB and SCC based Fast Circuit Partition Algorithm for Parallel SPICE simulation,” International Conference on ASIC (ASICON), pp.1247-1250, Oct. 2009.
  6. E. Pebesma and G. Heuvelink, “Latin Hypercube Sampling of Gaussian random fields,” Technometrics, Vol.41, No.4, pp.303-312, 1999. https://doi.org/10.2307/1271347
  7. C. Robert and G. Casella, Monte Carlo Statistical Methods, Springer, 2005.
  8. A. Singhee and R. Rutenbar, “From Finance to Filp flops: A Study of fast quasi-Monte Carlo methods from Computational finance applied to Statistical Circuit Analysis,” International Symposium on Quality Electronic Design (ISQED), pp.685-692, March 2007.
  9. Y. Xie and Y. Chen, “Statistical High-Level Synthesis under Process Variability,” IEEE Design and Test of Computers, Vol.26, No.4, pp.78-87, 2009. https://doi.org/10.1109/MDT.2009.85
  10. F. Wang, Y. Xie, and A. Takach, “Variation-aware Resource Sharing and Binding in Behavioral Synthesis,” Asia and South Pacific Design Automation Conference (ASP-DAC), pp.79-84, Jan. 2009.
  11. J. Jung and T. Kim, “Timing Variation-aware High-Level Synthesis Considering Accurate Yield Computation,” International Conference on Computer Design (ICCD), pp.207-212, Oct. 2009.
  12. L. Cheng, J. Xiong, and L. He, “Non-Linear Statistical Static Timing Analysis for Non-Gaussian Variation Sources,” Design Automation Conference (DAC), pp.250-255, June 2007.
  13. Y. Chen and Y. Xie, “Tolerating Process Variation in High-Level Synthesis Using Transparent Latches,” Asia and South Pacific Design Automation Conference (ASP-DAC), pp.73-78, Jan. 2009.
  14. C. Visweswariah, K. Ravindran, K. Kalafala, S. Walker, S. Narayan, D. Beece, J. Piaget, N. Venkateswaran, and J. Hemmett, “First-Order Incremental Block-Based Statistical Timing Analysis,” Computer-Aided Design of Integrated Circuits and Systems, Vol.25, Issue 10, pp.2170-2180, Oct. 2006. https://doi.org/10.1109/TCAD.2005.862751
  15. C. Hongliang and S. Sapatnekar, “Statistical timing analysis under spatial correlations,” Computer-Aided Design of Integrated Circuits and Systems, Vol.24, Issue 9, pp. 1467-1482, Sept. 2005. https://doi.org/10.1109/TCAD.2005.850834
  16. S. Tsukiyama, M. Tanaka, and M. Fukui, “A statistical static timing analysis considering correlations between delays,” Asia and South Pacific Design Automation Conference (ASP-DAC), pp.353-358, Jan 2001- Feb 2001.
  17. X. Li, J. Le, P. Gopalakrishnan, and L. Pileggi, “Asymptotic Probability Extraction for Nonnormal Performance Distributions,” Computer-Aided Design of Integrated Circuits and Systems, Vol.26, Issue 1, pp.16-37, Jan. 2007. https://doi.org/10.1109/TCAD.2006.882593
  18. S. H. Kulkarni, D. Sylvester, and D. Blaauw, “A Statistical Framework for Post-Silicon Tuning through Body Bias Clustering,” International Conference on Computer-Aided Design (ICCAD), pp.39-46, Nov. 2006.
  19. S. Bhardwaj, W. Wang, R. Vattikonda, Y. Cao, and S. Vrudhula, “Scalable model for predicting the effect of negative bias temperature instability for reliable design,” Circuits, Devices & Systems, IET, Vol.2, No.4, pp.361-371, 2008. https://doi.org/10.1049/iet-cds:20070225
  20. B. C. Paul, K. Kang, H. Kufluoglu, M. A. Alam, and K. Roy, “Temporal performance degradation under NBTI: Estimation and design for improved reliability of nanoscale circuits,” Design, Automation and Test in Europe (DATE), pp.780-785, Mar. 2006.
  21. D. R. Bild, G. E. Bok, and R. P. Dick, “Minimization of NBTI Performance Degradation Using Internal Node Control,” Design, Automation and Test in Europe (DATE), pp.148-153, Apr. 2009.
  22. M. B. da Silva, V. V. A. Camargo, L. Brusamarello, G. I. Wirth, and R. da Silva, “NBTI-aware technique for transistor sizing of high-performance CMOS gates,” Latin American Test Workshop (LATW), pp.1-5, Mar. 2009.
  23. B. Vaidyanathan, A.S Oates, Y. Xie, and Y. Wang, “NBTI-aware statistical circuit delay assessment,” International Symposium on Quality Electronic Design (ISQED), pp.13-18, Mar. 2009.
  24. R. Kanj, R. Joshi, C. Adams, J. Warnock, and S. Nassif, “An Elegant Hardware-corroborated Statistical Repair and Test Methodology for Conquering Aging Effects,” International Conference on Computer-Aided Design (ICCAD), pp.497-504, Nov. 2009.

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