The Transactions of the Korean Institute of Electrical Engineers P (전기학회논문지P)

The Korean Institute of Electrical Engineers (대한전기학회)
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The DWA Design with Improved Structure by Clock Timing Control

클록 타이밍 조정에 의한 개선된 구조를 가지는 DWA 설계

  • 김동균 (전북대학교 전자정보공학부) ;
  • 신홍규 (원광대학교 전자 및 제어공학부) ;
  • 조성익 (전북대학교 전자공학부)
  • Received : 2010.10.14
  • Accepted : 2010.11.09
  • Published : 2010.12.01
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Abstract

In multibit Sigma-Delta Modulator, DWA(Data Weighted Averaging) among the DEM(Dynamic Element Matching) techniques was widely used to get rid of non-linearity that caused by mismatching of unit capacitor in feedback DAC path. this paper proposed the improved DWA architecture by adjusting clock timing of the existing DWA architecture. 2n Register block used for output was replaced with 2n S-R latch block. As a result of this, MOS Tr. can be reduced and extra clock can also be removed. Moreover, two n-bit Register block used to delay n-bit data code is decreased to one n-bit Register. In order to confirm characteristics, DWA for the 3-bit output with the proposed DWA architecture was designed on 0.18um process under 1.8V supply. Compared with the existing architecture. It was able to reduce the number of 222 MOS Tr.

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References

  1. R. K. O. J. A. P. Nys, "Dynamic Element Matching Techniques with Arbitrary Noise Shaping Function," in Proc. ISCAS 96, Atlanta, vol. 1. pp. 293-296, May 1996.
  2. Fogleman and Ian Galton, "A Dynamic Element Matching Technique for Reduced- Distortion Multibit Quantization in Delta- Sigma ADCs," IEEE Tr.ansactions on Circuit and Systems, vol. 48, no. 2, pp.158-170, Feb. 2001. https://doi.org/10.1109/82.917784
  3. E. Radke, A. Eshraghi, and T. S. Feiz, "A 14-bit current-mode ${\Delta}{\sum}DAC$ based upon rotated dat weighted averaging," IEEE J. Solid-State Circuits, vol. 35, pp.1074-1084, Aug. 2000. https://doi.org/10.1109/4.859496
  4. A. A. Hamoui and K. Martin, "Linearity enhancement of multibit ${\sum}-{\Delta}$ modulator using pseudo data-weighted averaging," in Proc. IEEE ISCAS, pp. III 285-288, May 2002.
  5. Y. Greets, M. Steyaert, and W. Sansen, "A High-Performance Multibit ${\Delta}{\sum}$ CMOS ADC, " IEEE J. Solid-Stata Circuits, vol. SC-35, pp. 1829-1840, Dec. 2000.
  6. M. Miller et al., "A Multibit Sigma-Delta AD for Multimode Receivers," IEEE J. Solid-State Circuits, vol. 38, pp.475-482, Mar. 2003. https://doi.org/10.1109/JSSC.2002.808321
  7. 김선홍, 최석우, 조성익, 김동용, "Data Weighted Averaging을 이용한 3차 멀티비트 Sigma-Delta 변조기," 전자공학회논문지, 제41권, 제9호, 107-114쪽, 2004.
  8. A. A. Hamoui and K. Martin, "High-order multi-bit modulators and pseudo data-weighted averaging in low-oversampling ${\Delta}{\sum}$ ADCs for broad-band application," IEEE T. Circuits and Systems, vol.51, pp. 72-85, Jan. 2004. https://doi.org/10.1109/TCSI.2003.821291