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Design of Gate-Ground-NMOS-Based ESD Protection Circuits with Low Trigger Voltage, Low Leakage Current, and Fast Turn-On

  • Koo, Yong-Seo (Department of Electronic Engineering, Seokyeong University) ;
  • Kim, Kwang-Soo (Sogang Institute of Advanced Technology, Sogang University) ;
  • Park, Shi-Hong (Department of Electronics and Electrical Engineering, Dankook University) ;
  • Kim, Kwi-Dong (Convergence Components & Materials Research Laboratory, ETRI) ;
  • Kwon, Jong-Kee (Convergence Components & Materials Research Laboratory, ETRI)
  • Received : 2009.05.17
  • Accepted : 2009.09.14
  • Published : 2009.12.31
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Abstract

In this paper, electrostatic discharge (ESD) protection circuits with an advanced substrate-triggered NMOS and a gate-substrate-triggered NMOS are proposed to provide low trigger voltage, low leakage current, and fast turn-on speed. The proposed ESD protection devices are designed using 0.13 ${\mu}m$ CMOS technology. The experimental results show that the proposed substrate-triggered NMOS using a bipolar transistor has a low trigger voltage of 5.98 V and a fast turn-on time of 37 ns. The proposed gate-substrate-triggered NMOS has a lower trigger voltage of 5.35 V and low leakage current of 80 pA.

Keywords

References

  1. J.J. Yang, "Electrostatic Discharge Protection Circuit Employing MOSFETs Having Double ESD Implantations," U.S. Patent 6 040 603, Mar. 21, 2000.
  2. M.D. Ker and C.H. Chuang, "ESD Implantations in 0.18 $\mu$m Salicided CMOS Technology for On-Chip ESD Protection with Layout Consideration," Proc. Int. Symp. Physical and Failure Analysis of Integrated Circuits, 2001, pp. 85-90.
  3. K.H. Oh et al., "Analysis of Nonuniform ESD Current Distribution in Deep Submicron NMOS Transistors," IEEE Trans. Electron Devices, vol. 49, no. 12, Dec. 2002, pp. 2171-2182. https://doi.org/10.1109/TED.2002.805049
  4. T.Y. Chen and M.D. Ker, "Investigation of the Gate-Driven Effect and Substrate-Triggered Effect on ESD Robustness of CMOS Devices," IEEE Trans. Device Mater. Reliability, vol. 1, no. 4, Dec. 2001, pp. 190-203. https://doi.org/10.1109/7298.995833
  5. Jin-Young Choi, "AC Modeling of the ggNMOS ESD ProtectionDevice," ETRI Journal, vol. 27, no. 5, Oct. 2005, pp. 628-634. https://doi.org/10.4218/etrij.05.0104.0196
  6. T.Y. Kim et al., "Degradation Behavior of 850 nm AlGaAs/GaAs Oxide VCSELs Suffered from Electrostatic Discharge," ETRI Journal, vol. 30, no. 6, Dec. 2008, pp. 833-843. https://doi.org/10.4218/etrij.08.0108.0148
  7. O. Semenov et al., "Novel Gate and Substrate Triggering Techniques for Deep Sub-micron ESD Protection Devices," Microelectronics Journal, no. 37, no. 6, Sept. 2005, pp. 526-533. https://doi.org/10.1016/j.mejo.2005.07.019
  8. O. Semenov et al., ESD Protection Device and Circuit Design for Advanced CMOS Technologies, Springer, United States, 2008.
  9. J. Barth et al., "TLP Calibration, Correlation, Standards, and New Techniques," Proc. EOS/ESD Symp., 2000, pp. 85-96.
  10. W. Stadler et al., "Does the TLP Failure Current Obtained by Transmission Line Pulsing Always Correlate to Human Body Model Tests-" Proc. EOS/ESD Symp., 1997, pp. 336-372.
  11. G. Notermans, P. de Jong, and F. Kuper, "Pitfalls When Correlating TLP, HBM, and MM Testing," Proc. EOS/ESD Symp., 1998, pp. 170-176.

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