ETRI Journal

  • 제31권6호
  • /
  • Pages.725-731
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  • 2009
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  • 1225-6463(pISSN)
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  • 2233-7326(eISSN)
한국전자통신연구원 (Electronics and Telecommunications Research Institute)
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Design of Gate-Ground-NMOS-Based ESD Protection Circuits with Low Trigger Voltage, Low Leakage Current, and Fast Turn-On

  • Koo, Yong-Seo (Department of Electronic Engineering, Seokyeong University) ;
  • Kim, Kwang-Soo (Sogang Institute of Advanced Technology, Sogang University) ;
  • Park, Shi-Hong (Department of Electronics and Electrical Engineering, Dankook University) ;
  • Kim, Kwi-Dong (Convergence Components & Materials Research Laboratory, ETRI) ;
  • Kwon, Jong-Kee (Convergence Components & Materials Research Laboratory, ETRI)
  • 투고 : 2009.05.17
  • 심사 : 2009.09.14
  • 발행 : 2009.12.31
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초록

In this paper, electrostatic discharge (ESD) protection circuits with an advanced substrate-triggered NMOS and a gate-substrate-triggered NMOS are proposed to provide low trigger voltage, low leakage current, and fast turn-on speed. The proposed ESD protection devices are designed using 0.13 ${\mu}m$ CMOS technology. The experimental results show that the proposed substrate-triggered NMOS using a bipolar transistor has a low trigger voltage of 5.98 V and a fast turn-on time of 37 ns. The proposed gate-substrate-triggered NMOS has a lower trigger voltage of 5.35 V and low leakage current of 80 pA.

키워드

참고문헌

  1. J.J. Yang, "Electrostatic Discharge Protection Circuit Employing MOSFETs Having Double ESD Implantations," U.S. Patent 6 040 603, Mar. 21, 2000.
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피인용 문헌

  1. Improvement of electrostatic discharge current-handling capability for high-voltage multi-finger nLDMOS devices with self-triggered technique vol.35, pp.6, 2009, https://doi.org/10.1088/1361-6641/ab807d