Journal of Computing Science and Engineering

Korean Institute of Information Scientists and Engineers (한국정보과학회)
권호 표지
DOI QR코드

DOI QR Code

Hardware Platforms for Flash Memory/NVRAM Software Development

  • Nam, Eyee-Hyun (School of Computer Science and Engineering, Seoul National University) ;
  • Choi, Ki-Seok (H Project Team, SK Energy) ;
  • Choi, Jin-Yong (School of Computer Science and Engineering, Seoul National University) ;
  • Min, Hang-Jun (School of Computer Science and Engineering, Seoul National University) ;
  • Min, Sang-Lyul (School of Computer Science and Engineering, Seoul National University)
  • Published : 2009.09.30
Download PDF
⟨ Previous Next ⟩

Abstract

Flash memory is increasingly being used in a wide range of storage applications because of its low power consumption, low access latency, small form factor, and high shock resistance. However, the current platforms for flash memory software development do not meet the ever-increasing requirements of flash memory applications. This paper presents three different hardware platforms for flash memory/NVRAM (non-volatile RAM) software development that overcome the limitations of the current platforms. The three platforms target different types of host system and provide various features that facilitate the development and verification of flash memory/NVRAM software. In this paper, we also demonstrate the usefulness of the three platforms by implementing three different types of storage system (one for each platform) based on them.

Keywords

References

  1. BAN, A. 1995. Flash file system, US Patent, no. 5,404,485.
  2. Cirrus Logic. 2006. EDB9315A engineering development board, http://www.cirrus.com/en/pubs/manual/EDB9315A_Tech_Ref_Manual.pdf.
  3. DOUGLIS, F., R. CACERES, F. KAASHOEK, K. LI, B. MARSH AND J. TAUBER. 1994. Storage alternatives for mobile computers. In Proceedings of the 1st Symposium on Operating Systems Design and Implementation (OSDI):25-37.
  4. HA, Y., J. YI, H. HORII, J. PARK, S. JOO, S. PARK, U. CHUNG AND J. MOON. 2003. An edge contact type cell for phase change RAM featuring very low power consumption. 2003 Symposium on VLSI Technology: 175-176. https://doi.org/10.1109/VLSIT.2003.1221142
  5. HWANG, C. 2003. Nanotechnology enables a new memory growth model. In Proceedings of the IEEE 91(11):1765-1771. https://doi.org/10.1109/JPROC.2003.818323
  6. Intel. 1998. Understanding the flash translation layer (FTL) specification. http://developer.intel.com.
  7. JO, H., J. KANG, S. PARK, J. KIM AND J. LEE. 2006. FAB: flash-aware buffer management policy for portable media players. IEEE Transactions on Consumer Electronics 52(2):485-493. https://doi.org/10.1109/TCE.2006.1649669
  8. KIM, B., S. CHO AND Y. CHOI. 2004. OneNAND (TM): a high performance and low power memory solution for code and data storage. In Proceedings of the 20th Non-Volatile Semiconductor Memory Workshop.
  9. LAWTON, G. 2006. Improved flash memory grows in popularity. Computer 39(1):16-18. https://doi.org/10.1109/MC.2006.22
  10. National Instruments. What is data acquisition. http://www.ni.com/dataacquisition/whatis.htm.
  11. Aleph One. 2002. YAFFS: yet another flash file system. http://www.yaffs.net.
  12. PARK, S., D. JUNG, J. KANG, J. KIM AND J. LEE. 2006. CFLRU: a replacement algorithm for flash memory. In Proceedings of the 2006 international conference on compilers, architecture and synthesis for embedded systems. Seoul, Korea: 234-241. https://doi.org/10.1145/1176760.1176789
  13. Sourceforge.net. PRAMFS: protected and persistent RAM file system. http://pramfs.sourceforge.net.
  14. Samsung Electronics. NAND flash memory data sheets. http://www.samsung.com.
  15. SEONG, Y., E. NAM, J. YOON, H. KIM, J. CHOI, S. LEE, Y. BAE, J. LEE, Y. CHO AND S. MIN. 2009. Hydra: a block-mapped parallel flash memory solid-state disk architecture. Accepted for publication in the IEEE Transactions on Computers.
  16. SHEIKHOLESLAMI, A. AND P. GULAK. 2000. A survey of circuit innovations in ferroelectric randomaccess memories. In Proceedings of the IEEE 88(5):667-689. https://doi.org/10.1109/5.849164
  17. TEHRANI, S., J. SLAUGHTER, E. CHEN, M. DURLAM, J. SHI AND M. DEHERREN. 1999. Progress and outlook for MRAM technology. IEEE Transactions on Magnetics 35(5):2814-2819. https://doi.org/10.1109/20.800991
  18. WOODHOUSE, D. 2001. JFFS: the journalling flash file system. In Proceedings of Ottawa Linux Symposium.
  19. Xilinx. MicroBlaze processor reference guide. http://www.xilinx.com/support/documentation/sw_manuals/mb_ref_guide.pdf.
  20. Xilinx. Virtex-4 family overview. http://direct.xilinx.com/support/documentation/data_sheets/ds112.pdf.
  21. Xilinx. Spartan-3 FPGA family data sheet. http://direct.xilinx.com/support/documentation/data_sheets/ds099.pdf.
  22. YOON, J., E. NAM, Y. SEONG, H. KIM, B. KIM, S. MIN AND Y. CHO. 2008. Chameleon: a high performance flash/FRAM hybrid solid state disk architecture. IEEE Computer Architecture Letters 7(1):17-20 https://doi.org/10.1109/L-CA.2007.17

Cited by

  1. Hydra: A Block-Mapped Parallel Flash Memory Solid-State Disk Architecture vol.59, pp.7, 2010, https://doi.org/10.1109/TC.2010.63
  2. Ozone (O3): An Out-of-Order Flash Memory Controller Architecture vol.60, pp.5, 2011, https://doi.org/10.1109/TC.2010.209
  3. An Optimal Allocation Algorithm of Adjustable Delay Buffers and Practical Extensions for Clock Skew Optimization in Multiple Power Mode Designs vol.32, pp.3, 2013, https://doi.org/10.1109/TCAD.2012.2220769