참고문헌
- Y. Cui, X. Duan, J. Hu, C. M. Lieber, "Doping and Electrical Transport in Silicon Nanowires," J. Phys. Dhem. B Vol. 104, Num. 22, pp. 5213-5216, Jun. 2000 https://doi.org/10.1021/jp0009305
- J. Y. Yu, S. W. Chung, J. R. Heath, "Silicon Nanowires: Preparation, Device Fabrication, and Transport Properties," J. Phys. Chem. B, Vol. 104, pp. 11864-11870, 2000 https://doi.org/10.1021/jp002595q
- Y. Cui, C. M. Lieber, "Nanoscale Electronic Devices Assembled Using Silicon Nanowire Building Blocks," Science, Vol. 291, pp. 851-853 Feb. 2001 https://doi.org/10.1126/science.291.5505.851
- Y. Cui, Z. Zhong, D. Wang, W. U. Wang, C. M. Lieber, "High Performance Silicon Nanowire Field Effect Transistors," Nano Lett. Vol.3, pp. 149-152, Jan. 2003 https://doi.org/10.1021/nl025875l
- Y. Cui, L. Lauhon, Gudiksen J, Wang M. S., C. M. Lieber, "Diameter-controlled synthesis of single-crystal silicon nanowires," Appl. phys. Lett., Vol. 78, Number 15, pp. 2214-2216, Apr. 2001 https://doi.org/10.1063/1.1363692
- Agrawal B., De. V. K., Meindl J. D., "Device parameter optimization for reduced short channel effects inretrograde doping MOSFET's," IEEE Transactions on electron devices, Vol. 43, Issue 2, pp. 365-368, Feb 1996 https://doi.org/10.1109/16.481743
- Effendi Leobandung, Jian Gu, Lingjie Guo, and Stephen Y. Chou, "Wire-channel and wrap-around gate metal-oxide-semiconductor field-effect transistors with a significant reduction of short channel effects," J. Vac. Sci. Technol. B, Vol. 15, Issue 6, pp. 2791-2794, Nov. 1997 https://doi.org/10.1116/1.589729
- Balestra F., Cristoloveanu S., Benachir M., Brini J., Elewa T., "Double-Gate Silicon-on-Insulator Transistor with Volume Inversion: A New Device with Greatly Enhance Performance," IEEE electron device letters, Vol 8, Number 9, pp. 410-412, Sep. 1987 https://doi.org/10.1109/EDL.1987.26677
- Doyle B. S., Datta S., Doczy M., Hareland S., Jin B., Kavalieros J., Linton T., Murthy A., Rios R., Chau., R., "High Performance Fully-Depleted Tri-Gate CMOS Transistors," IEEE electron device letters, Vol. 24, Number 4., pp. 263-265 , Apr. 2003 https://doi.org/10.1109/LED.2003.810888
- M. Bescond K. Nehari, J. L. Autruan, N. Cavassilas, D. Munteanu, and M. Lannoo, "3D quantum-modeling and simulation of multi-gate nano MOSFETs," in Prco, IEDM Tech. Dig, pp. 617-620, Dec. 2004
- D. Munteanu, "3D Quantum Numerical Simulation of Single-Event Transients in Multiple-Gate Nanowire MOSFETs," Nuclear Science, Vol. 54, No. 4, pp. 994-1001, Aug. 2007 https://doi.org/10.1109/TNS.2007.892284
- Umeno A., Hirakawa K., "Fabrication of atomic-scale gold junctions by electrochemical plating using a common medical liquid", Appl. Phys. Lett., Vol.86, 143103, Mar. 2005 https://doi.org/10.1063/1.1897444
- S. H. Hong, M. G. Kang, H. Y. Cha, M. H. Son, J. S. Hwang, H. J. Lee, S. H. Sull, S. W. Hwang, D. Whang, and D. Ahn, "Fabrication of one-dimensional devices by a combination of AC dielectrophoresis and electrochemical deposition", Nanotechnology, Vol. 13, pp. 105305, Feb. 2008