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Design of a DI model-based Content Addressable Memory for Asynchronous Cache

  • Battogtokh, Jigjidsuren (Department of Computer and Communication Engineering, Chungbuk National University) ;
  • Cho, Kyoung-Rok (Department of Computer and Communication Engineering, Chungbuk National University)
  • Published : 2009.06.30

Abstract

This paper presents a novel approach in the design of a CAM for an asynchronous cache. The architecture of cache mainly consists of four units: control logics, content addressable memory, completion signal logic units and instruction memory. The pseudo-DCVSL is useful to make a completion signal which is a reference for handshake control. The proposed CAM is a very simple extension of the basic circuitry that makes a completion signal based on DI model. The cache has 2.75KB CAM for 8KB instruction memory. We designed and simulated the proposed asynchronous cache including CAM. The results show that the cache hit ratio is up to 95% based on pseudo-LRU replacement policy.

Keywords

References

  1. Jih-Kwon Peir, W.W. Hsu, A.J.Smith, "Functional implementation techniques for CPU cache memories," IEEE Computers, Vol.48, Feb. 1999, pp. 100-110. https://doi.org/10.1109/12.752651
  2. J. Tuominen, T. Santti, J. Plosila, "Comparative Study of Synthesis for Asynchronous and Synchronous Cache Controllers," IEEE Norchip conference, March. 2006, pp. 11-14. https://doi.org/10.1109/NORCHP.2006.329233
  3. S.S. Guillory, D.G. Saab, A.Yang, "Fault modeling and testing of self-timed circuits," IEEE Chip-to-System Test Concerns for the 90's, April. 1991, pp. 62-66. https://doi.org/10.1109/VTEST.1991.208134
  4. Jin-Fu Li, "Testing Ternary Content Addressable Memories With Comparison Faults Using March-Like Tests," IEEE Computer-Aided design of integrated circuits and systems, Vol.26, No. 5, May. 2007, pp. 919-931. https://doi.org/10.1109/TCAD.2006.884415
  5. Kuo-Hsing Cheng, Chia-Hung Wei, Shu-Yu Jiang, " Static divided word matching line for low-power content addressable memory design," IEEE Circuits and Systems ISGAS, Vol.2, May. 2004, pp. 629-632. https://doi.org/10.1109/ISCAS.2004.1329350
  6. Jien-Chung Lo, " Fault-tolerant content addressable memory," IEEE Proc. ICCD, Oct. 1993, pp.193-196. https://doi.org/10.1109/ICCD.1993.393382
  7. R.E. Aly, B.R. Nallamilli, M.A. Bayoumi, " Variable-way set associative cache design for embedded system applications," Circuits and Systems MWSCAS, Vol.3, Dec. 2003, pp.1435-1438. https://doi.org/10.1109/MWSCAS.2003.1562565
  8. V. Chaudhary, T.-H. Chen, F. Sheerin, L.T. Clark, "Critical race-free low-power nand match line content addressable memory tagged cache memory," Computers and Digital Techniques, IET, Vol.2, Jan. 2008, pp.40-44. https://doi.org/10.1049/iet-cdt:20070040
  9. Kuo-Hsing Cheng, Chia-Hung Wei, Shu-Yu Jiang, "Static divided word matching line for low-power content addressable memory design," Circuits and Systems ISCAS, Vol.2, May. 2004, pp.929-632.
  10. J.G. Delgado-Frias, A. Yu, J. Nyathi, "A dynamic content addressable memory using a 4-transistor cell," Design of Mixed-Mode Integrated Circuits and Applications, Vol.2, Aug. 1999, pp.110-113.
  11. T. Kumaki, Y. Kouno, M. Ishizaki, T. Koide, H.J Mattausch, "Application of Multi-ported CAM for Parallel Coding," Circuits and Systems APCCAS, Vol.3, Dec. 2006, pp.1859-1862.

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  1. Design of an Asynchronous Instruction Cache based on a Mixed Delay Model vol.10, pp.3, 2010, https://doi.org/10.5392/JKCA.2010.10.3.064