Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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Low-Power ECG Detector and ADC for Implantable Cardiac Pacemakers

이식형 심장 박동 조율기를 위한 저전력 심전도 검출기와 아날로그-디지털 변환기

  • Published : 2009.03.31
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Abstract

A wavelet Electrocardiogram(ECG) detector and its analog-to-digital converter(ADC) for low-power implantable cardiac pacemakers are presented in this paper. The proposed wavelet-based ECG detector consists of a wavelet decomposer with wavelet filter banks, a QRS complex detector of hypothesis testing with wavelet-demodulated ECG signals, and a noise detector with zero-crossing points. To achieve high-detection performance with low-power consumption, the multi-scaled product algorithm and soft-threshold algorithm are efficiently exploited. To further reduce the power dissipation, a low-power ADC, which is based on a Successive Approximation Register(SAR) architecture with an on/off-time controlled comparator and passive sample and hold, is also presented. Our algorithmic and architectural level approaches are implemented and fabricated in standard $0.35{\mu}m$ CMOS technology. The testchip shows a good detection accuracy of 99.32% and very low-power consumption of $19.02{\mu}W$ with 3-V supply voltage.

본 논문에서 이식형 심장 박동 조율기를 위한 심전도 검출기와 아날로그-디지털 변환기(ADC)를 설계한다. 제안한 웨이블렛 심전도 검출기는 웨이블렛 필터 뱅크 구조의 웨이블렛 변조기, 웨이블렛 합성된 심전도 신호의 가설 검정을 통한 QRS 신호 검출기와 0-교차점을 이용한 잡음 검출기로 구성된다. 저전력 소모의 동작을 유지하며 보다 높은 검출 정확도를 갖는 심전도 검출기의 구현을 위해, 다중스케일 곱의 알고리즘과 적응형의 임계값을 갖는 알고리즘을 사용하였다. 또한 심전도 검출기의 입력단에 위치하는 저전력 Successive Approximation Register ADC의 구현을 위해, 신호 변환의 주기 중, 매우 짧은 시간 동안에만 동작하는 비교기와 수동 소자로 구성되는 Sample&Hold를 사용하였다. 제안한 회로는 표준 CMOS $0.35{\mu}m$ 공정을 사용하여 집적 및 제작되었고, 99.32%의 높은 검출 정확도와 3V의 전원 전압에서 $19.02{\mu}W$의 매우 낮은 전력 소모를 갖는 것을 실험을 통해 확인하였다.

Keywords

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