References
- S. Mangard, M. Aigner and S. Dominikus, "A Highly Regular and Scalabel AES Hardware Architecture," IEEE Transactions on Computer, Vol. 52, No.1, pp. 483-491, April, 2004. https://doi.org/10.1109/TC.2003.1190589
- D. Josephson and S. Poehhnan, "Debug methoology for the McKinley processor," International Test Conference, pp. 451-460, Baltimore, MD. USA, Oct. 30- Nov.1, 2001.
- R. Kapoor, "Security vs. test quality: Are they mutually exclusive?" International Test Conference, pp. 1414, Charlotte, NC, USA, Oct. 26-28, 2004. https://doi.org/10.1109/TEST.2004.1387422
- J. Lee, M. Teharanipoor, and J. Plusquellic, "A Low-Cost Solution for Protecting IPs Against Scan-Based Side-Channel Attacks," VLSI Test Symposium, pp. 94-99, Berkeley, CA, USA, Apr. 30-May 4, 2006. https://doi.org/10.1109/VTS.2006.7
- B. Yang, K. Wu and R. Karri, "Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard," International Test Conference, pp. 339-344, Charlotte, NC, USA, Oct. 26-28, 2004. https://doi.org/10.1109/TEST.2004.1386969
- S. Paul, R. S. Chakraborty and S. Bhunia, "VImScan : A Low Overhead Scan Design Approach for Protection of Secret Key in Scan-Based Secure Chips," VLSI Test Symposium, pp. 455-460, Berkeley, CA, USA, May 6-10, 2007. https://doi.org/10.1109/VTS.2007.89
- B. Yang, K. Wu and R. Karri "Secure Scan : A Design-for-Test Archiecture for Crypto Chips," IEEE Transaction Computer-Aided Design of Integrated Circuits and systems, Vol. 25, No. 10, pp. 2287-2293, Oct. 2006. https://doi.org/10.1109/TCAD.2005.862745
- W. Stallings, "Cryptography and Network Security, " Englewood Cliffs, NJ : Prentice-Hall, 2003.