Collision-free Interleaver Composed of a Latin Square Matrix for Parallel-architecture Turbo Codes

병렬 처리 구조 터보 부호에서 라틴 방진 행렬로 구성된 충돌 방지 인터리버

  • 김대선 (연세대학교 전기전자공학과 부호 및 정보이론 연구실) ;
  • 오현영 (삼성전자) ;
  • 송홍엽 (연세대학교 전기전자공학과 부호 및 정보이론 연구실)
  • Published : 2008.02.28

Abstract

In the parallel-architecture turbo codes, the constituent interleaver must avoid memory collision. This paper proposes a collision-free interleaver structure composed of a Latin square matrix and pre-designed interleavers. Our proposed interleavers can be easily optimized for various information block sizes and for various degrees of parallelism. Their performances were evaluated by computer simulation.

병렬 처리 구조 터보 부호에서 메모리 충돌을 피하기 위한 구성 인터리버 설계가 필요하다. 본 논문에서는 기존에 설계된 인터리버들과 라틴 방진 행렬로 구성된 충돌 방지 인터리버를 제안한다. 제안된 인터리버는 다양한 블록 길이와 다양한 병렬 처리 차수에 대하여 쉽게 최적화 할 수 있다. 제안된 인터리버의 성능을 컴퓨터 모의실험을 통해 검증하였다.

Keywords

References

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