Journal of information and communication convergence engineering

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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Clock Routing Synthesis for Nanometer IC Design

  • Jin, Xianzhe (Department of Information and Communication Engineering, Hanbat National University) ;
  • Ryoo, Kwang-Ki (Department of Information and Communication Engineering, Hanbat National University)
  • Published : 2008.12.31
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Abstract

Clock skew modeling is important in the performance evaluation and prediction of clock distribution network and it is one of the major constraints for high-speed operation of synchronous integrated circuits. In clock routing synthesis, it is necessary to reduce the clock skew under the specified skew bound, while minimizing the cost such as total wire length and delay. In this paper, a new efficient bounded clock skew routing method is described, which generalizes the well-known bounded skew tree method by allowing loops, i.e., link-edges can be inserted to a clock tree when they are beneficial to reduce the clock skew and/or the wire length. Furthermore, routing topology construction and wire sizing is used to reduce clock delay.

Keywords

References

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