대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

Telescopic 증폭기를 이용한 고속 LVDS I/O 인터페이스 설계

Design of a High-Speed LVDS I/O Interface Using Telescopic Amplifier

  • 발행 : 2007.06.25
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

본 논문은 3.3V, $0.35{\mu}m$ CMOS 기술을 이용하여 I/O 인터페이스를 설계, 검증하였다. LVDS (low-voltage differential signaling)는 차동전송 방식과 저 전압의 스윙으로 저 전력 고속의 데이터를 전송할 수 있다. 본 논문은 기존의 차동증폭기나 감지 증폭기를 사용한 LVDS와 달리 telescopic 증폭기를 이용하여 2.3 Gbps의 빠른 전송속도를 갖는 LVDS 고속 인터페이스를 구현하였다. LVDS의 표준을 모두 충족하였고 25.5mW의 전력소모를 갖는다. 이 회로는 삼성 $0.35{\mu}m$ CMOS 공정을 이용하여 설계하였으며, HSPICE를 통하여 검증하였다.

This paper presents the design and the implementation of input/output (I/O) interface circuits for 2.5 Gbps operation in a 3.3V 0.35um CMOS technology. Due to the differential transmission technique and low voltage swing, LVDS(low-voltage differential signaling) has been widely used for high speed transmission with low power consumption. This interface circuit is fully compatible with the LVDS standard. The LVDS proposed in this paper utilizes a telescopic amplifier. This circuit is operated up to 2.3 Gbps. The circuit has a power consumption of 25. 5mW. This circuit is designed with Samsung $0.35{\mu}m$ CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

키워드

참고문헌

  1. IEEE Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI), 1596.3 SCI-LVDS Standard, IEEE Std. 1596.3-1996, 1994
  2. Electrical characteristics of low-voltage differential-signalling (LVDS) interface circuits, TIA/EIA-644, National Semiconductor Corp., ANSI/TIA/EIA, 1996
  3. A. Boni, A. Pierazzi, and D. Vecchi, 'LVDS I/O interface for Gb/s-per-Pin Operation in 0.35$\mu$m CMOS', IEEE Journal of Solid-State Circuits, vol. 36, pp. 706-711, April 2001 https://doi.org/10.1109/4.913751
  4. K. Gulati and H. S. Lee, 'A High-Swing CMOS Telescopic Operational Amplifier', IEEE Journal of Solid-State Circuits, vol. 33, no. 12, December 1998
  5. Unekawa, Y, et al. 'A 5 Gb/s 8$\times$8 ATM switch element CMOS LSI supporting five quality-of-service classes with 200 MHz LVDS interface', Solid-State Circuits Conference, 1996. Digest of Technical Papers. 43th ISSCC., 1996 IEEE International 8-10 Feb. 1996 Page(s):118-119, 428
  6. M. Chen, J. Silva-Martineez, M. Nix, and M. E. Robinson, 'Low-Voltage Low-Power LVDS Drivers', IEEE Journal of Solid-State Circuits, vol. 40, No. 2, February 2005
  7. G. Mandal and P.Mandal, 'Low-Power LVDS Receiver for 1.3 Gbps Physical Layer (PHY) Interface', IEEE International Symposium, on 23-26, pp. 2180-2183, May 2005